Arria II GX configuration from CPLD

[nome]

Hello,

I am using the JS28F256M29EWH NOR Flash with only using 8-bit data and 25-bit address Parallel Flash in FPP mode. In my case, our flash 8-bits flash data pins are directly connected with fpga_config_data's 8-bit pins. Mostly, these pins I recognize are connected with CPLD, and another set of CPLD pins is connected with fpga_config_data for configuration.

I am following the instructions from ug_pfl.pdf to convert our .SOF to .POF. For NOR Flash programming, I am using the PFL Mega core IP in Mode "only Flash programming" from Arria II FPGA I check read back by using  option bits 

Now, I am attempting to configure Arria II GX with CPLD EPM240T100I5 without PFL using Config_Control_Codes from Intel Altera Stratix II.

Please find the attached file.

The issue is that the code doesn't work. I am checking fpga_dclk and fpga_nSTATUS pins using an oscilloscope, but no activity is showing. This implies that there might be a problem with RESET_n and MAX_EN as given in the VHDL Codes.

Also, I have defined unused pins as "As Output Ground"

Please help me identify where I am making a mistake.

Thanks,

Nome

[NurAiman_M_Intel]

Hi,

Thank you for contacting Intel community.

What do you mean by "configure Arria II GX with CPLD EPM240T100I5 without PFL using Config_Control_Codes from Intel Altera Stratix II"? What is the reason on using Config_Control_Codes from Intel Altera Stratix II for Arria ii?

What Quartus version do you used?

Any error shows?

Regards,

Aiman

[nome]

Hello,

Thank you for your reply.

What do you mean by "configure Arria II GX with CPLD EPM240T100I5 without PFL using Config_Control_Codes from Intel Altera Stratix II? 

I am not utilizing PFL (parallel flash loader) due to the limited LE (logic element) blocks available, as the EPM240T100I5 CPLD has only 240 blocks. This restriction prevents the use of a higher-density CPLD.

We need to allocate more space for various functionalities, aside from FPGA configuration. This is why we are using the official config_control_codes from Stratix, as indicated in the attached QAR file in my initial post.

All specific pin requirements, such as fpga_addr, fpga_nSTATUS, fpga_dclk, and others, have been assigned according to our custom board specifications. However, the issue is that these codes are not working; when testing fpga_dclk from the oscilloscope, it remains low at all times.

Thanks,

Nome

[NurAiman_M_Intel]

Hi,

• Is JTAG working fine? (without config control codes)
• Where did you get the Config control codes? Is it from Intel or other source?
• Can you provide us your schematic?

[nome]

Hi,

Thanks for your Reply 

                           Is JTAG working fine? (without config control codes)                                                                                                                                                                                       Yes Excellent Working i can get CPLD and  FPGA in quartus programmer even I can get Flash when I load as per our board pins assignment PFL (prallel flash loader) .sof file into FPGA can easily flash programming .

                                Where did you get the Config control codes? Is it from Intel or other source?                                                                                                                                     yes From Intel official site

Thanks 

Nome

[NurAiman_M_Intel]

Hi,

Please provide the link to the Config_control code page so we can do the checking.

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Any update for this case?

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

[nome]

 Hello,

I apologize for the delayed response due to my long vacations.

Please find attached our configuration area schematic pdf .

Could you please assist me in identifying any errors, such as incorrect addresses entities?

I'm uncertain about the correctness of the configuration. also suggest us if i will consider PFL  prallel flash loader 

Best Regards,

Thanks 

Nome