I am used DDR Controller of Arria V.
I known that DDR Controller PHY's Calibration have 4 Stages.
Stage1. Read calibration part one - DQS enable calibration and DQ/DQS contering
Stage2. Write calibration part one - leveling
Stage3. Write calibration part two - DQ/DQS centering
Stage4. Read calibration part two - Read latency minimization
But I known that Arria V is not supported Write Leveling at DDR Controller Calibration.
So then, What does 'Calibration Sequencer of Arria V DDR Controller PHY' doing at 'stage2 Write Leveling'?
The calibration process flow is generic explanation. For unique case like Cyclone V and Arria V that doesn't support leveling calibration, the particular calibration process will be skipped.