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Hi,
How can I print the preloader output to HPS_UART1 instead of HPS_UART0?
There are two UART defined in qsys and currently the preloader prints to UART0.
Thanks
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Hi bsp_user,
The u-boot open source link can be found as below:
https://github.com/altera-opensource/u-boot-socfpga
I not sure about the u-boot preloader related part but for u-boot, the related device tree for Arria v can be found as below, can try to search with the key word socfpga_ with the product family name, it includes sockpga.dtsi:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.10/arch/arm/dts/socfpga.dtsi
The uart0 and uart1 address for Arria v HPS as below:
uart0 and uart1 may not share the same physical pin connection and you might need to consider additional hardware in order to get the uart logging. Do check with the pin guidlines of the device and also check in the pin mux and peripherals setting under the Arria V HPS IP in quartus qsys on how the default uart0 was enabled by default. If uart1 selection is not found together with the same pin used by uart0 then need to search for other pins which allows uart1 pinmux routing.
Thanks.
Regards,
Aik Eu
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Hi bsp_user,
I never change the preloader code before and how it was set to use the HPS UART1 as the default. It may be hard coded as most HPS UART0 from different family board also using the address 0xFFC02000.
you will need to check the preloader code and set the HPS UART1 serial address as 0xFFC03000 in order to make the effective changes.
Thanks.
Regards,
Aik Eu
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Before you close it,
Since its my first time using UBOOT, maybe its possible for you to refer me to the relevant files/folders? maybe additional sentence or two regarding its source structure and relevance to the Arria V HPS?
Thank you
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Hi bsp_user,
The u-boot open source link can be found as below:
https://github.com/altera-opensource/u-boot-socfpga
I not sure about the u-boot preloader related part but for u-boot, the related device tree for Arria v can be found as below, can try to search with the key word socfpga_ with the product family name, it includes sockpga.dtsi:
https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.10/arch/arm/dts/socfpga.dtsi
The uart0 and uart1 address for Arria v HPS as below:
uart0 and uart1 may not share the same physical pin connection and you might need to consider additional hardware in order to get the uart logging. Do check with the pin guidlines of the device and also check in the pin mux and peripherals setting under the Arria V HPS IP in quartus qsys on how the default uart0 was enabled by default. If uart1 selection is not found together with the same pin used by uart0 then need to search for other pins which allows uart1 pinmux routing.
Thanks.
Regards,
Aik Eu
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Hi bsp_user,
Welcome! I am closing this thread for now.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Thanks.
Regards,
Aik Eu
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