Custom IP from a verilog code

[Sijith]

Hi,

I could make a custom IP from a verilog module counter.v (attached with this message). It have clock, reset, avalon_ready as input ports and data and avalon_valid as output ports.  This is designed to act as an avalon streaming source port. But when I open component editor and add my sysnthesis file (which is counter.v), then I am getting some error messages as shown in attachnment ComponentEditor1.PNG. From the message, it seems that the component editor see my code as it contains an avalon memory map slave port (see ComponentEditor2.PNG also). Is it a normal behavior and is there any specific reason for the component editor to assume my code have a memory map slave port (in reality, it does not have one).  I changed the parameters as shown in ComponentEditor3.PNG (please compare ComponentEditor2.PNG andComponentEditor3.PNG to see the changes in the parameter I made). I am inviting the attention of experts to verify what I have done is correct?

[sstrell · Accepted solution]

The component editor mis-identified your component as an agent instead of a streaming source, so that's why the errors appeared.  You fixed the errors by defining the interfaces and signal roles so you are good to go.  To avoid this from happening in the future, in your code use the 3-part naming scheme for interface signals discussed in the Platform Designer user guide: <interface type>_<interface name>_<defined signal role>.  This automates how Component Editor identifies the signals in your design.

[Sijith]

Thank you for making things clear!

[SyafieqS]

Glad your issue had been addressed. Let me know if there is any other concern from your end

[SyafieqS]

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