Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18972 Discussions

Arria10 EPCQL512 remote update.

Honored Contributor II

I am trying to make remote update work on my board with Arria10 10AS066H2F34I1SG and EPCQL512. 


From the user guide 15.3.2: Nios II HAL Driver A Nios II HAL driver will be developed similar to the driver’s currently available for CFI (altera_avalon_cfi_flash) and EPCS (altera_avalon_epcs_flash_controller). 


And then a link to how to make your own HAL driver. 


If i open the *_MEM_BASE with alt_flash_open_dev it seams that writing and reading is working. When I look at an example called Remote System Upgrade over UART based on Nios II Processor with EPCQ (Cyclone V E FPGA Development Kit) the driver is not used and the flash is accessed directly through IORD and IOWR. If I look at another example called Board Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit) another way of accessing the flash is used from flash_qspi.{c,h}. Can the usual driver from alt_flash be used or not? 


Regardless of how I do the writing to flash I am not able to make remote update work. If i modify the example for the Cyclone I get problems with generating the JIC file because the SOF overlaps something called Boot info or Reserved Option Bits and it gives this error message. The requested address range for page_0 (0x00000000 - 0x00E5D7DF) overlaps with the address range for Reserved Option Bits (0x00000000 - 0x00000020). What is this Boot info that I only see when adding a SOF for Arria10 and how does it affect remote update? By placing the factory image at a later address, I have tried 0x20, 0x100 and 0x1000 I can make a JIC file with user and factory and reconfigure between them, but when I update the user image in flash it always falls back to the factory image after trying to load the user image. How should I generate the RPD to make it work? I also tried to port the Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit) example to my board, but so far I have not been able to make it work. Every time it start it corrupts one byte in zipfs so the next time it starts it can no longer find the files. The example is very confusing, is there a reason why it updates PFL (parallel flash loader?) option bits in flash? Is there a simple example somewhere demonstrating remote update with Arria10 and EPCQL?
0 Kudos
2 Replies
Honored Contributor II



The HAL driver (alt_flash) should works since you're able to read/write without issues. Both design examples are demonstrating different ways to access the controller register but they're indeed using the same methodology. The IORD/IOWR is pretty straightforward accessing controller registers directly. The HAL provides API to read/write the flash and those APIs are using IORD/IOWR to access the registers as well. 


For Arria 10, the address range (0x0 - 0x20) is reserved for Option Bits. Make sure your factory SOF/hardware image is placed after 0x20 and the configuration should works. Please make sure your user image/application works before you put them together into one single JIC file and perform reconfiguration.
Honored Contributor II

Thank you, it is working now.