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Altera_Forum
Honored Contributor I
735 Views

amazing behavior of FPGA

Hi all, 

i am using 5CGTFD5C5F27C7 to implement a data acquisition system, and the Quartus version is 14.0.0 Build 200 06/17/2014 SJ Full Version. 

 

i grasped an amazing result with signalTap, which made me be bewildered (http://www.baidu.com/link?url=wwrxh9stom5c5xcypfcoipl3jml8w-6u8xy2ihrvxxmzi9tdlgbqima6c1pbej205dtj09...). 

 

https://alteraforum.com/forum/attachment.php?attachmentid=14801&stc=1  

 

please https://alteraforum.com/forum/attachment.php?attachmentid=14801&stc=1 refer to the attached image, the corresponding code is as follows: 

 

 

if(~rst_n) y_lines<=0; 

else if(y_lines==z_lines) y_lines<=0; 

else if((cnt_wr_unit[3:0]==write_units[3:0])&(|write_units[3:0])) y_lines<=y_lines+1'b1; 

else y_lines<=y_lines; 

 

From the signalTap, when y_lines adds 1, cnt_wr_unit is 0 and write_units is 1, so why y_lines parameter is triggered add operation? 

all signals (cnt_wr_unit, write_units, y_lines) are located in the same module and are driven by the same clock(no clock crosssing issue). 

TQ does not report any timing violations for these signals either. 

 

can anyone explain this phenomenon?  

 

B&W, 

ingdxdy
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1 Reply
Altera_Forum
Honored Contributor I
18 Views

Can you post the whole code, not just a snippet?