Arrow SOCkit DDR3 SDRAM controller?

[Altera_Forum]

Has anyone written a DDR3 SDRAM controller for the FPGA side of the SOCkit that they are willing to share? Or has anyone build a 'facade' type hardware component for the uniphy to allow it to be accessed as simply as the avalon mm slave interface? 

 I've been trying to use the hard controller 'uniphy' but its pretty much over my head I think. I got something to build, by taking the Uniphy setup in qsys and connecting it to the HPS axi master, but it doesn't work (written data is not read back). I've not really got any idea how to debug that. The Uniphy part came from a working example. The HPS part came from a working example. Even if I do get it working I'd need to make my simple master into an axi master I think - which looks as complicated as writing a controller!

[Altera_Forum]

Have you looked at this design yet? http://www.rocketboards.org/foswiki/projects/sockitvideoipvipreferencedesign I don't think you want to attempt to create a memory controller since that would be way more work than using what already exists. When adding the Uniphy IP to your design make sure you read the user guide info that discusses the steps. It's not difficult to use but if you don't use the provided steps then I guarantee the design won't compile or the interface won't work properly. 

 You don't need to use AXI for your own IP. If you connect a mix of Avalon and AXI components Qsys will adapt between them. The only thing it won't be able to adapt are features that are supported in AXI but are not available in Avalon. If you haven't created a memory master before I would look at some examples (or maybe just use them). The Qsys tutorial has some masters that you stream data in and out of them and they connect to memory. You could also look at the master blocks in this design which have more features than the Qsys tutorial but they have better documentation: http://www.alterawiki.com/wiki/modular_sgdma. There are probably quite a few other mastering IP that you can take a look at up on the Altera wiki to borrow/use as a template.

[Altera_Forum]

Thanks. Do you mean this guide or is there a simpler version? http://www.altera.com/literature/hb/external-memory/emi_tut_qdr.pdf. The one I found is bigger than the data sheets for the old DDR SDRAM, hopefully there is something more digestible.  

 The reference design for the video server looks useful. Thanks for the pointer. I'll download now and have a look through.  I'd taken this working example and ripped out the DMA stuff, just connecting the HPS to the SDRAM. https://github.com/zhemao/ddr3_dma_demo.  Great to hear I don't need to use AXI. If there is a simpler Avalon MM style master I can use then that will be much simpler. In terms of clocks can my avalon mm master have its own clock or does it need to use the Uniphy one?

[Altera_Forum]

Thanks. The video server reference design looks very helpful. 

 The path I'd tried was taking this and I ripped out the DMA stuff/connected it to the HPS axi master. https://github.com/zhemao/ddr3_dma_demo  Great to hear I don't need to use a full AXI master. The avalon MM interface is much simpler and if I can use that, with my choice of clock, to connect to uniphy that would be very helpful.   Do you mean these uniphy docs:uniphy design flow tutorials; external memory ... - altera (http://www.google.ch/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0cciqfjaa&url=http%3a%2f%2fwww.altera.com%2fliterature%2fhb%2fexternal-memory%2femi_tut_qdr.pdf&ei=yxvavjljj4kzpjt8gige&usg=afqjcnfhebp5elylq45yi-rkev__5tnwpq&sig2=vpe0osexki7ooviqimwygg&bvm=bv.83829542,d.zwu). Or is there a simpler version, that document is quite substantial/confusing to me!

[Altera_Forum]

I think the master templates that were posted to the altera wiki are probably the least complex. I'm not sure if they are highly tuned but the ones in the Qsys tutorial are very fast. All you would have to do is connect logic to them that tells them where to start reading/write, transfer length, and some control bits. This info is communicated via Avalon-ST which is a streaming protocol with a simple ready-valid handshake. 

 You can use whatever clock frequency you like. If the master is on a different clock domain than the memory controller slave port Qsys will insert clock crossing logic. My recommendation if you care about throughput to make sure the master is either on the same clock domain as the memory controller slave port or higher. Typically the memory slave port doesn't operate at a high frequency because by the time the data has been presented it has undergone a bunch of half rate conversions (half the clock, twice the width). So as long as you make the master wide enough you can saturate the memory bandwidth.  That's the correct Uniphy doc, you can probably focus on the Qsys section since that's the flow applicable to your design.