Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
19664 Discussions

Assignment RTL_PARAMETER

fst21
Beginner
254 Views
Hello, I use the PLL Reconfig Intel FPGA IP core for Arria 10, which uses one fifo each for data and command synchronization. These fifos are mapped as block RAM in M20K despite the small size of only 144 bits. My goal is to use MLAB memory for this. Unfortunately, with Quartus 22.3 the ram_block_type parameter of the sc_fifos is not passed to the toplevel of the PLL Reconfig IP, so that a change via a QSF assignment seems to be the most sensible way. The following assignment was not successful although the assignment editor recognizes this as correct and Quartus does not issue an error message or warning: set_instance_assignment -name RTL_PARAMETER "ram_block_type=\"MLAB\"" -to gen_AccSocketPLL[0].inst_SocketPLLReconfig|pll_reconfig_0|reconfig.reconfig_core.iopll_reconfig_core_inst|command_fifo|scfifo_component -entity NallatechA10385A_HWFramework Does anyone have any idea how the assignment has to be formulated correctly? Or how the goal can be achieved with a different method? Thanks you very much, Fritjof
0 Kudos
1 Solution
RichardTanSY_Intel
128 Views

As it turns out, there's no way to change it other than changing the Verilog code. 

Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.


Regards,

Richard Tan



View solution in original post

8 Replies
RichardTanSY_Intel
216 Views

RTL_parameter is mostly used for PR design flow. I don't think it is applicable in this case.

Reference:

https://www.intel.com/content/www/us/en/docs/programmable/683296/21-4/designpartitionassignmentsrtlp...

https://www.intel.com/content/www/us/en/docs/programmable/683834/22-2/method-2-set-qsf-assignment-fo...


For generated IP, one way that I can think of is to add the RAM_BLOCK_TYPE defparam in the fifo entity/module of the iopll reconfig ip (in this case, I add the parameter in the verilog file altera_iopll_reconfig_core.v of the pll_reconfig_0.ip file).

example:

defparam

scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB";


Hope that works for you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


RichardTanSY_Intel
194 Views

May I know does my latest reply helps ?


Best Regards,

Richard Tan


fst21
Beginner
178 Views

Hello Richard,

thank you for your answer.

Yes, the change scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB"; works. I had already tried this. However, it is not applicable, because every time the IP is generated, this line has to be added manually.

In the article https://community.intel.com/t5/FPGA-Wiki/Using-set-parameter-for-Quartus-compile-directives-in-VHDL-... a similar problem is described. Only unfortunately it is unclear how this would work with a string.

Many greetings,
Fritjof

RichardTanSY_Intel
166 Views

I will need to consult the engineering team for alternative way to do it. I am not able to success map it to MLAB using set_parameter as well.

fyi set_parameter how-to use:

https://www.intel.com/content/www/us/en/docs/programmable/683432/22-1/tcl_pkg_project_ver_7-0_cmd_se...

 

Best Regards,

Richard Tan

 

RichardTanSY_Intel
139 Views

Just to inform you that I am still pending response from the engineering team.


Regards,

Richard Tan


RichardTanSY_Intel
129 Views

As it turns out, there's no way to change it other than changing the Verilog code. 

Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.


Regards,

Richard Tan



fst21
Beginner
110 Views

That is a great pity. Hopefully it will work in a future release!

 

Regards,

Fritjof

RichardTanSY_Intel
77 Views

Would like to clarify that there is currently no plan to enhance this IP unless there is a good justification and demand from the customers.


With that, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


Reply