CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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yes I have defined a clock for "clk", as you see in the picture. I have another project with the same settings and it works. Don't know what is wrong. Maybe someone had the same issue and got it solved? I use Quartus 8.1
You need to write an SDC file to constrain your design. At a minimum it defines the clock, but also things like false paths, multicycle paths, IO delays etc.. Read this tutorial here:
