Hello,We are using Cyclone IV EP4CE40F23I7 and we have an implementation for an interface to a DSP (ADSP-21489, AMI Interface), which is causing us some problems with timing. The fact is that our implementation is using asynchronous edge detection through a latch, as show in picture 1. We are aware that this is probably not the best implementation but is the one that allows us to achieve the required access times and it is working stable so far. With this solution we need a lot of timing constraints to relate the signals in both domains and be sure that we have the correct timing in our signals. We have done this combining “set_net_delays” on our sdc and some “GetMaxTimingPath” checks on a Tcl that we run after timing analysis (although there are probably best techniques to constraint signals in different clock domains). We do not always get good results in these checks, as they are not affecting routing. We would like to simplify and improve this implementation but at the same time we are trying to keep the access times as low as they are now. So we are analyzing different possibilities:
@mfbm,Shouldn't you have two flip-flops in the new domain to handle the clock crossing? One flip-flop will leave you with problems of metastability. My best guess is that this is your current problem. Also, for my own reference, how fast is this interface supposed to work? Perhaps another approach would be more appropriate and easier? Dan
Thanks for the reply!Yes, we know that to avoid metastability problems the best solution is not to use the signals before a 2 flip-flop stage. The question is more about the implementation in picture 1: is this stable enough, taking into account that one of the flip-flops in the chain is in rd_strobe domain and the second one in clk_sys domain? Wouldn't implementation 1 and 2 have the same response in terms of metastability? Adding a third flip-flop in implementation 2 would solve metastability issues but will delay the accesses in comparison to implementation 1, as they will be detected with clk_sys edge and not inmediately with the edge of rd_strobe. We are working at 10 ns in the FPGA and supposed to achieve 90 ns mean read accesses (of 32 bit data which means 2 consecutive DSP accesses).