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Auto increment address in the memory in a verilog program

Mathiazhagan
Novice
839 Views

Hi there, 

Am a new learner in verilog, So please help me out how to resolve this issue

I have created a simple SRAM Module 

I want to increment my address on posedge of every clock pulse, but i don't know how to do it, so anyone please help me out in resolving this issue 

I have posted my verilog code too 

module sramw(dataIn,dataOut,Addr,CE,WE,OE,RD,Clk,RST,//count
);
parameter ADR = 19;
parameter DAT = 8;
parameter DPTH = 524288;
//parameter COUNT = 19;
input [DAT-1:0] dataIn;
output reg [DAT-1:0] dataOut;
input [ADR-1:0] Addr;

input CE,
WE,
RD,
Clk,
RST,
OE;
//reg Addr
//internal variables
reg [DAT-1:0] SRAM [DPTH-1:0];
always @ (posedge Clk)
begin
if (CE == 1'b0) begin
if (WE == 1'b0 && RD == 1'b0) begin
SRAM [Addr] = dataIn;
end
else if (RD == 1'b1 && WE == 1'b1) begin
dataOut = SRAM [Addr];
end
else;
end
else;
end
endmodule

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7 Replies
ak6dn
Valued Contributor III
824 Views

Well, you haven't shown enough code.

In your module definition Addr[ADR-1:0] is an input to the module and thus is a set of wires.

In a higher level module that instantiates a call to sramw() you would probably have declared Addr[ADR-1:0] as a reg.

And in that module you could do assignments to that reg variable, including incrementing it on a clock edge.

Mathiazhagan
Novice
792 Views

Dear Sir/Madam,

                     Yes as you mentioned the addr[ADR-1:0] has been assigned as input, but the input cannot be declared as a register right, then how to solve the issue.

 

 

On a condition @ every posedge clk my address should get auto incremented and in that auto incremented address i have to store some value.

If possible could u please share me a code for this ,Which will be very much useful for me to proceed further.

 

With Regards,

V.Mathiazhagan 

ak6dn
Valued Contributor III
732 Views

You still need to write the upper level module code that instantiates your sramw module instance.

It would have pieces of code that look something like this:

module TEST;

localparam ADR = 9;

reg clk;
reg [ADR-1:0] addr;

always @(posedge clk) addr <= addr + 1;

sramw #(.ADR(ADR)) u1 (.Clk(clk), .Addr(addr), ...);

endmodule TEST;

 Now this is obviously not complete code, but it gives an idea of what you have to do.

I've left out how you generate the clk signal, and obviously you need to setup some values at initialization or on reset asserted.

But the above shows what your 'auto incrementing' address signal needs to look like.

YEan
Employee
803 Views

Hi,


Do you have any updates on your problem?


Thanks,

Ean


Mathiazhagan
Novice
792 Views

Dear Ean,

No, I did not get any update for this problem, I have tried but i could not solve the problem, could u please share me a sample code for the above mentioned problem, which will be very much useful for me to proceed further.

Awaiting for your favorable response.

 

 

With Regards,

V.Mathiazhagan

YEan
Employee
702 Views

The example provided by @ak6dn  had shown the auto increment of address using always block.

YEan
Employee
688 Views

Hi,


We do not receive any response from you to the previous question that have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Regards,

Ean


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