Am a new learner in verilog, So please help me out how to resolve this issue
I have created a simple SRAM Module
I want to increment my address on posedge of every clock pulse, but i don't know how to do it, so anyone please help me out in resolving this issue
I have posted my verilog code too
parameter ADR = 19;
parameter DAT = 8;
parameter DPTH = 524288;
//parameter COUNT = 19;
input [DAT-1:0] dataIn;
output reg [DAT-1:0] dataOut;
input [ADR-1:0] Addr;
reg [DAT-1:0] SRAM [DPTH-1:0];
always @ (posedge Clk)
if (CE == 1'b0) begin
if (WE == 1'b0 && RD == 1'b0) begin
SRAM [Addr] = dataIn;
else if (RD == 1'b1 && WE == 1'b1) begin
dataOut = SRAM [Addr];
Well, you haven't shown enough code.
In your module definition Addr[ADR-1:0] is an input to the module and thus is a set of wires.
In a higher level module that instantiates a call to sramw() you would probably have declared Addr[ADR-1:0] as a reg.
And in that module you could do assignments to that reg variable, including incrementing it on a clock edge.
Yes as you mentioned the addr[ADR-1:0] has been assigned as input, but the input cannot be declared as a register right, then how to solve the issue.
On a condition @ every posedge clk my address should get auto incremented and in that auto incremented address i have to store some value.
If possible could u please share me a code for this ,Which will be very much useful for me to proceed further.
You still need to write the upper level module code that instantiates your sramw module instance.
It would have pieces of code that look something like this:
module TEST; localparam ADR = 9; reg clk; reg [ADR-1:0] addr; always @(posedge clk) addr <= addr + 1; sramw #(.ADR(ADR)) u1 (.Clk(clk), .Addr(addr), ...); endmodule TEST;
Now this is obviously not complete code, but it gives an idea of what you have to do.
I've left out how you generate the clk signal, and obviously you need to setup some values at initialization or on reset asserted.
But the above shows what your 'auto incrementing' address signal needs to look like.
No, I did not get any update for this problem, I have tried but i could not solve the problem, could u please share me a sample code for the above mentioned problem, which will be very much useful for me to proceed further.
Awaiting for your favorable response.
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