I attempt to implement an oscillator inside FPGA using verilog loop. Since delays of 4 LUT inputs(a, b ,c ,d) vary, it's necessary to assign signals to specified LUT inputs to ensure the design is controllable. The code is as follows:
module Signal_Oscillator_P(
input iSIG,
output POSE
);
wire VCC=1'b1;
wire combout;
cycloneii_lcell_comb \SIGNAL (
.datad(iSIG),
.dataa(VCC),
.datab(POSE),
.datac(VCC),
.combout(combout));
defparam \SIGNAL .sum_lutc_input = "datac";
defparam \SIGNAL .lut_mask = "3300";
lcell u(combout,POSE);
endmodule
However, Quartus drifts off my attempts. The fitting result in chip planner indicates a different routing from the expected, 'POSE' is assigned to datad and 'iSIG' is assigned to datac. Since it's terrible to modify my design with ECO every time I finished compliation, I am seeking for an easy method to ensure the final fitting result matches my verilog code.
