How to change value set for powerdown in P1 state of PCI Express design?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

How to change value set for powerdown in P1 state of PCI Express design?

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Doing reference design of PCI Express design as per "ip compiler for pci express" (https://www.altera.com/literature/ug/ug_pci_express.pdf). After running simulation of the design for 212 ns got stuck with Error "Illegal value of powerdown in p1 state". How can I rectify this problem?

http://www.alteraforum.com/forum/attachment.php?attachmentid=10993&stc=1

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