RF filter with FPGA / CPLD

[Altera_Forum]

Hello to all. 

first of all I hope not wrong section of this forum. I studied electronics, I know very well for C ++ and assembly MCU. in recent times I have found out what are the FPGA and CPLD, then I found some cheap cards made by Altera I found a card with low-cost MAX II EPM240. I became interested in FPGA because I wanted to make a circuit that works in RF.   my question is very simple: it is possibile to create a band-pass filter in radio frequency from 0 to 30 MHz with this technology?     I apologize for my little English knowledge. I await to your support, thank you very much

[Altera_Forum]

yes. Depends on your fpga sampling rate support. Modern fpgas can achieve speeds say 200MHz ~ 400MHz. so a cut off point at 0 ~ 30MHz is possible. But Why do you think this is band pass, it is low pass filter. You will need adc suitable to capture the analogue signal then apply filter.

[Altera_Forum]

many thanks for the quick response 

I have thought of using FPGA to create a low pass filter or high-pass that can be programmed externally by MCU.  I thought about using this http://www.ebay.it/itm/altera-fpga-cpld-programmer-usb-blaster-compatible-lc-maxii-epm240-dev-board-/141315924702?var=&hash=item20e715e2de"]http://www.ebay.it/itm/altera-fpga-cpld-programmer-usb-blaster-compatible-lc-maxii-epm240-dev-board-/141315924702?var=&hash=item20e715e2de%22]http://www.ebay.it/itm/altera-fpga-cpld-programmer-usb-blaster-compatible-lc-maxii-epm240-dev-board-/141315924702?var=&hash=item20e715e2de (http://www.ebay.it/itm/altera-fpga-cpld-programmer-usb-blaster-compatible-lc-maxii-epm240-dev-board-/141315924702?var=&hash=item20e715e)  like you said, there are models that reach 200/400mhz but that of the link on the PCB has a crystal from 50mhz I wonder if the speed of the quartz corresponds to that of the sampling rate or the integrated circuit has another internal clock faster?  last question : the fpga they process only digital pins? I have to add an external ADC?

[Altera_Forum]

You need adc at a sampling speed compatible with RF signal. 

You need fpga rather than cpld as you will require high speed and plenty of dsp resource depending on filter taps. crystal speed can be low as there are PLLs inside fpgas to generate high frequencies.

[Altera_Forum]

I read that MAX II EPM240, is a CPLD so I tried an FPGA but I wanted confirmation from those who know more than me. 

can I use a development board using Altera CYCLONE II ep2c5t144 to create RF filters?

[Altera_Forum]

You will need to see if the board has an ADC with a speed suitable to RF sampling requirement(sampling rule or undersampling). Then you will need to estimate your dsp requirements. I understand cyclone has 150 multipliers or so. You need to see how many taps you want and if you can go above signal speed to share resource.

[Altera_Forum]

Some FPGAs have an ADC built in but it probably isn't going to provide the dynamic range and SNR that you want for a receiver application; read the specs carefully. While you probably want a higher end ADC for your front end, an internal ADC might get you started to prove your concept at low cost.  

 Watch out for aliasing. You will need an analog AAF on the front end before your ADC. A while back I worked on a design where we used the FPGA as the IF mixer and could select channels digitally. It was a fun project.

[Altera_Forum]

I installed Quartus II for linux, I read some tutorials to make the first examples. 

as I have suggested before to buy my FPGA I need to know the number of taps for my program. you have any tips on how to learn what I need to create an RF filter?  thanks again for your help, I hope not to disturb too much

[Altera_Forum]

Start by googling "FPGA low pass filter".