Hi all,In short: I have two identical interfaces, but Qsys tells me the slave is outside the master's address range. I don't understand what's going on and why they would be different. Both have the address unit set to WORDS not SYMBOLS. So they should be the same(?) I recieve this error in Qys that tells me the slave is addressable with 29 bits, and the master with a weird partial 29 bits. error: <master interface>: <slave interface> (0x0..0x1fff ffff) is outside the master's address range (0x0..0x11ff ffff)
However, they are identical, and in component editor, both interfaces have the address unit in WORDS, and bits per symbol as 8 bits. I listed them below (the point is they are identical). The interfaces are address[23:0], data[143:0], and byteenable[17:0]. avalon-mm (master): avm_mem_write avm_mem_read avm_mem_address[23:0] avm_mem_writedata[143:0] avm_mem_readdata[143:0] avm_mem_waitrequest avm_mem_response[1:0] avm_mem_byteenable[17:0] avalon-ms (slave): avs_s0_write avs_s0_read avs_s0_address[23:0] avs_s0_writedata[143:0] avs_s0_readdata[143:0] avs_s0_waitrequest avs_s0_response[1:0] avs_s0_byteenable[17:0] Any help with understanding with what's going on I would be grateful. There have been other times that this has confused me a bit, so if you can make it clear, I would appreciate! I also attached photos if they help.
Just an update. Daixiwen (post# 5 at http://www.alteraforum.com/forum/showthread.php?t=33226) has a really good short explanation of addressing.In addition, I just found out (after a couple months of looking into this) that what I was doing is illegal...that's why the behavior seemed odd. All my other interfaces (32b and 64b) with exact matching Master-Slave data widths are able to connect without problem, except this 144-bit one. As per the Avalon -MM specification, however, data widths must be a power of 2 (from 8 to 1024)!