Avalon MM - using a FIFO with a registered output

[SKon1]

Hello,

I have an Avalon MM interface of which I'm the master.

The data that I want to write to the slave is buffered in a FIFO.

To achieve better timing - I want to use a FIFO with a registered output...but it seems impossible with Avalon MM.

This is because the "waitrequest" Avalon MM signal. 

Consider the following scenario:

1. The data bus of the master side uses a FIFO with 2 pipeline stages on the output.

2. The user logic sees the waitrequest signal de-asserted so it starts reading data out of the FIFO.

3. Suddenly the waitrequest signal is asserted and because of the pipeline latency - by the time data gets to the slave it's lost.

I know the AXI standard uses "Register Slices" to handle such scenarios - but what about Avalon ?

[Kenny_Tan]

I look into the fifo in the quartus ip catalog vs the platform design ip catalog. Both of them are different where in the quartus ip catalog have addition option to add in the output register to have better timing. the Can you try to add pipeline register at the avalon in the qsys fifo and see how it behaves? If it does not get better means this would be the limitation of the design. We can help to file enhancement on this.

[Kenny_Tan]

Is there an update?

[SKon1]

Sorry,

I won't be having access to a simulator in the near future so I'm unable to test what you suggested.

But in my opinion - this is a VERY fundamental question about the Avalon bus and how it operates. Someone from Intel should be able to answer right away. without resorting to simulation or functional testing.

[Kenny_Tan]

If you want to get better timing, use Avalon pipelined bridge. It will add in the register for you for the operation. We do not have register slices in the platform designer. If you so happened want to convert Xilinx AXI interface with the register slices, you can use AXI bridge IP for it.

[SKon1]

Consider the following scenario:

I use an Avalon Pipeline bridge and connect the output of my FIFO to the input of the bridge.

I compile the design and see a timing violation on the data path between the output of the FIFO and the Input to the bridge.

How would you solve the problem then ?

[Kenny_Tan]

Then you can add another Avalon pipeline bridge then if it really happened.