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Hello,
I have an Avalon MM interface of which I'm the master.
The data that I want to write to the slave is buffered in a FIFO.
To achieve better timing - I want to use a FIFO with a registered output...but it seems impossible with Avalon MM.
This is because the "waitrequest" Avalon MM signal.
Consider the following scenario:
1. The data bus of the master side uses a FIFO with 2 pipeline stages on the output.
2. The user logic sees the waitrequest signal de-asserted so it starts reading data out of the FIFO.
3. Suddenly the waitrequest signal is asserted and because of the pipeline latency - by the time data gets to the slave it's lost.
I know the AXI standard uses "Register Slices" to handle such scenarios - but what about Avalon ?
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Sorry,
I won't be having access to a simulator in the near future so I'm unable to test what you suggested.
But in my opinion - this is a VERY fundamental question about the Avalon bus and how it operates. Someone from Intel should be able to answer right away. without resorting to simulation or functional testing.
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Consider the following scenario:
I use an Avalon Pipeline bridge and connect the output of my FIFO to the input of the bridge.
I compile the design and see a timing violation on the data path between the output of the FIFO and the Input to the bridge.
How would you solve the problem then ?
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Then you can add another Avalon pipeline bridge then if it really happened.

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