Avalon MM: writedata and write

[Altera_Forum]

Hi, a beginner's question, when passing data from HPS to the FPGA I use the AVALON MM interface. Now I'm a bit in doubt, if it is better to check "write" and then fetch "writedata" into a reg (verilog), e.g.: 

  module something( ... input write, input writedata, ... ); ... reg algo_in; ... always @(posedge clk)begin ... if(write)begin algo_in <= writedata; end ...   or if it is better to wire "writedata" directly, e.g.:  // module same as above ... wire algo_in; assign algo_in = writedata; ...   Do I actually need to check "write" for an avalon mapped slave interface, I saw that in tutorials it is done. But it seems to work using wires, too?!

[Altera_Forum]

If you want your logic to retain the value that has been written for a period of time greater than the brief time when 'write' is being asserted, then yes you would want to store it in a register. 

 If your logic doesn't care (for example, because 'algo_in' feeds to 'algo_out' and that result gets latched), then using a wire as you have done is fine.

[Altera_Forum]

Initially, I did check "write". I struggled for about 15 days with it not upcoming in my setup. I had everything connected in QSYS together with a toplevel file, but it never worked. Eventually I figured out, not checking for "write", and my setup works perfectly since I did receive the data, though. I call this data "writedata", also AVALON MM and slave. I think I understand your point about retaining data or just connecting the wires i.e. using "reg" or "wire", however I don't grok why I receive "writedata" and no "write"!? And what is the sense of checking for an additional "write"? 

 In a summary, why checking for "write" anyway if it works perfectly w/o it?

[Altera_Forum]

--- Quote Start ---  In a summary, why checking for "write" anyway if it works perfectly w/o it?  --- Quote End ---    Short of posting your module and testbench, post simulation or signaltap waveform showing your problem?  The general problem sounds like your _hw.tcl is not in agreement with your .v as far as timing of the signals goes.

[Altera_Forum]

Hi, thank you for answering so fast. Well, in the meanwhile I figured out, it was a timing issue: I gave an explicit "start" signal and checked then for "write", but "write" arrived before "start" due to the setup.  

 Still, my curiosity is rather to understand, why I should check for "write" as a signal at AVALON MM? What may happen if I don't check this?

[Altera_Forum]

I guess theres different ways to do it, but I believe that by far the simplest and most straight forward way to know when your module is being written to is to examine the 'write' or 'write_n' signal.