I am writting here to ask something about burst bit error rate test. I wonder whether you can tell me how can you solve the burst clock and data recovery, or you have a better solution than the burst mode CDR. Since we have a project that we need to deal with the GPON/EPON OLT upstreams,which rate at 1244Mbps or 2488Mbps. We need to recovey the clock and data from the upstreams,and put the low speed data and clock to the FPGA, so can you give some advise or other solutions.
Thanks!
