I have a PCBA that is setup in the following manner with the D[7:0] not going through the CPLD but rather is in a "flyby" type configuration. The FPGA (C10 GX) FPGA code has a Nios in it that runs from the FLASH after the FPGA is configured. Not using a PFL in the CPLD, its a design we have used in the past.
I program the FLASH through JTAG using a MFG code load for the FPGA (that simple has PFL module in it). I create a combined pof using the convert programming files loaded with a HEX file for the FPGA and one for the NIOS code. To create the HEX file for the FPGA ahead of time I used convert programming files to convert the sof to .hexout (with addr offset 0x0A0_0000) then renamed to .hex. I can program the FLASH with this combined pof file and it says success in programming he FLASH.
At that point if I manually load the FPGA using the sof from JTAG the Nios boot fine as it can read its code from the FLASH. That works every time.
However, when trying to parallel load the FPGA from FLASH using the CPLD, the FPGA asserts STATUS_N low about 300k DCLKs into the configuration. So this fails, same way each time. I looked at the combined POF file and it looks like it has content starting at the FPGA offset (in this case 0x0A0_0000).
I also simulated (the fully synchronous) CPLD code and it looks like it starts at the correct address offset ( 0x0A0_0000) in FLASH for the FPGA programming info and continues onward. I have chck the schematic address and data line pinouts. I used a logic analyer to look at DCLK, STATUS_N, CONFIG_N, STATUS_N. I am getting read with probes on D[7:0], address is difficult to probe on the board (but the NIOS boots/runs fine) so pretty sure its good.
Any thoughts on what might be going wrong. File conversion issue? Thank you.
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Hello,
I am sorry for late replying you.
I need to understand your setup.
- no PFL is used.
- data pins directly connected from flash to FPGA(Cyclone 10 GX).
From Cyclone 10 GX user guide, PS/FPP (MSEL mode = 000) the flash is only connected to CPLD, not directly to FPGA. CPLD will handle the data transaction during configuration. For your setup, how this is handled?
The flash programming is successful because Quartus connected to CPLD via JTAG and CPLD directly connected to Flash.
To configure FPGA from flash, CPLD need to handle all the configuration signals. This is where your setup fail.
From previous experience, most common mistake from users is the option bits generated for FPGA is not the same with what has been set into CPLD/Flash. You can check in the .map report file after Quartus compilation to compare.
regards,
Farabi
