I'm trying to implement two high-speed LVDS channels with SERDES logic on the U484 package (Cyclone 10 GX) together with 1866 MHz DDR3L. The problem is that the package has only three banks for high-performance links (3V bank doens't support this), and each LVDS channel requires its own bank due to the IOPLL restriction (each bank has its own IOPLL, and each SERDES based link requires an IOPLL). Can I directly use the external clock for the SERDES modules and generate the coreclk (1/8) in the SERDES modules, or is there a way to use an IOPLL from another bank?
Thank you, Dominik
Kindly find the below info and I request to you to follow the guidelines which is suggested from Intel.
The IOPLL restriction is different for transmitter and receiver.
For transmitter :
TX channels can span three adjacent banks, driven by the IOPLL in the middle bank.
Have to use IOPLL from same bank,
Kindly find the reference for the above in page no: 38 from the below document.