CLK Pins Positive or Negative Edge

[Altera_Forum]

Hello People, 

 I have 3 questions about CLK input pins.  1-  I see that there are 16 CLK pins on the EP3C25E144 fpga. On the Pin Planner, i see that some of them are positive edge, some of them are negative edge. What is the difference? do we have to use negative edged CLK input as "negedge" in the always block and positive edged CLK input as "posedge" in the always block?  On my previous design, i had not noticed this point and had used only CLK1. it looks negative edged and i was using it as posedge on my verilog design.  compiler did not give any error about this and design worked well. and now i have a doubt. if i had used as negedge, it would work better? or this would not effect?  2-  I have seen on some design shematics that single crystal oscillator output was connected to more than one CLK input pins of the fpga. is this a correct usage? and what is the intention here?  3- What should we do about the unused CLK input pins? leave unconnected or connect to VCCIO or GND? Which is the right way?  Thanks and Best Regards..

[Altera_Forum]

1 - IIRC you should only care if you are using a differential I/O standard for the clock input, and then one pin is the positive input and the other one is negative. If you use a single ended signal you can use any clock input as you wish. 

2 - no idea 3 - they should be tied to a stable voltage, either VCCIO or GND. If you leave them floating they could oscillate and cause excessive power drain on the I/O bank.

[Altera_Forum]

Thanks very much Daixiwen, 

 What about the second question? any comments from other guys?

[Altera_Forum]

Connecting CLK source to multiple inputs has been necessary up to Cyclone II family, if you wanted to drive more than one PLL. Starting with Cyclone III, the clock can be routed internally. Jitter or clock skew requirements can still suggest to connect multiple inputs in some cases.

[Altera_Forum]

hmm. 

 Yes, it was cyclone II, terasic board schematics.  Thanks !..