CPLD I/O's during power up

[Altera_Forum]

Hello everybody, 

 I am using a Max II EPM570T100A5 CPLD; in our design the CPLD controls 4 MOSFET drivers for a fullbridge, thus it is critical that these outputs on the CPLD remain at GND during system power up. On our board we have installed 10k Ohms pull downs to GND at these output pins believing this would do the trick. However when I power the board up these outputs still climb along with VDD as the device powers up, evidently the internal pullups on these I/O's is stronger and wins out.  What can I set on these I/O's in Quartus to avoid this problem ? Am I using the right resister pulldown values ?  Thanks a bunch in advance, Eric

[Altera_Forum]

Thinking about the problem should clarify, that Quartus can't control the state of unconfigured IOs, because this state is exclusively determined by the MAX II hardware. 

 The minimum and maximum weak pull-up values are specified in the datasheet. Depending on the threshold of the connected devices, you'll need 1 to 2.2k pull-down resistors for safe low-level during power up.

[Altera_Forum]

Ok, yes that makes sense, thanks FvM, I will give both of those resistor values a try. 

 Cheers, Eric

[Altera_Forum]

For a safe design, you should put in minimum pull-up resistor value from the datasheet and maximum acceptable low-level of the interfaced peripheral.