[CPLD MAX 10] Connecting the internal oscillator clock to the input of PLL

Altera_Forum · ‎03-06-2015

Hello,

So I wish to utilise the internal oscillator of the CPLD MAX10 as the clock source in my system.

The minimum clock frequency that the oscillator can output is 55MHz (it's a 10M08), which is too high for me (I need a clock that is less than 50MHz), so I let it go through a PLL.

 osc    osc_inst ( // Internal oscillator    
    .oscena ( 1'b1 ),
    .clkout ( in_clk )
    );
    
pll_mod    pll_mod_inst ( // PLL
    .areset ( sys_rst ),
    .inclk0 ( in_clk ),
    .c0 ( clk ),
    .locked ( pll_locked )
    );

And I got an error 15065:

error (15065): clock input port inclk[0] of pll "pll_mod:pll_mod_inst|altpll:altpll_component|pll_mod_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another pll, optionally through a clock control block

I have tried to go through a clock control block (ALTCLKCTRL) before going into PLL too, but still got the same error.

Can anyone help me with this?

Thanks.

Altera_Forum · ‎03-19-2015

in the "MAX 10 Clocking and PLL User Guide"

section 3-2 "Internal Oscillator Design Considerations"

"You cannot drive the PLLs with internal oscillator."

i think that is the reason.

integrate a oscillator in a fpga is a great progress, but if it can not be connected to a pll, the internal oscillator can not be used in most case.

i do not know why