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CYCLONE V HPS JTAG Boundary Scan - DDR RAM

ieeeHuseyin
Beginner
1,353 Views

Hello,

I want to perform JTAG boundary scan on CYCLONE V (5CSEBA2U23I7SN).

There is DDR3 RAM (MT41K64M16TW-107) on the board, connected to the HPS (Hard Processor System) side.

How can I perform DDR3 RAM testing via the JTAG port of the HPS (Hard Processor System)?

For example, I can access the SPI flash (connected to the HPS side) integrated on the board via JTAG using the following command.

"quartus_hps.exe -c1 -o S"

Is there a similar script for DDR RAM?

 

Thanks,

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JingyangTeh
Employee
1,267 Views

Hi ieeeHuseyin


I believe the tool you are looking for is the System Console.

You could read or write the memory address using the tool.

Please refer to the links below:

https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/introduction-to-system-console.html

https://www.intel.com/content/www/us/en/programmable/customertraining/webex/Adv_Qsys_SysCon_p2/System_Console.pdf


Regards

Jingyang, Teh


ieeeHuseyin
Beginner
1,245 Views

Thanks for your help. I will examine the documentation for the system console.

Well, it is mentioned in the link I provided below that DDR RAM can be controlled via JTAG boundary scan. Do I need to use an IP core to do this, or can it be done with bit-banging?

https://www.asset-intertech.com/wp-content/uploads/2020/09/testing-ddr3-memory-boundary-scan-jtag.pdf 

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JingyangTeh
Employee
1,165 Views

Hi


For the system console usage you would need to add in an soft IP to bridge the connection.

The soft IP required is the jtag-to-host soft IP.

Please refer to link below for more info for the soft IP.


https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/spi-agent-jtag-to-host-bridge-cores-48170.html


Regards

Jingyang, Teh


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JingyangTeh
Employee
1,132 Views

Hi


Any update on this case?

Do you have any more question regarding this case?


Regards

Jingyang, Teh


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ieeeHuseyin
Beginner
1,126 Views

Hi,

 

Well, is there any way to use the SDRAM Controller Subsystem via the JTAG interface without using the system console?

 

In the link I provided below, I am talking about SDRAM control with openocd.

 

Is it possible to achieve such control?

 

Thanks.

 

https://community.arm.com/support-forums/f/architectures-and-processors-forum/54872/cyclone-v---hps---ddr-ram-control-over-jtag-with-openocd 

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ieeeHuseyin
Beginner
1,105 Views

I conducted some experiments as shown below.

 

However, I couldn't access the SDRAM controller subsystem completely.

 

Which registers do I need to configure to access the SDRAM controller subsystem via JTAG?
Is there a register list available for this purpose?

All registers are available in the link below.

However, which registers do I need to configure?

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html 

 

 

openocd sdram controlopenocd sdram control

 

 

Thanks.

 

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JingyangTeh
Employee
852 Views

Hi


There is no ready configuration by Intel on the openocd ram control tool that you are using.

However it is possible the JTAG connection is the Cyclone V JTAG supports the IEE1149.1 standard.

You would need to add the JTAG UART Core IP on your design. Then through the IP you could access the SDRAM.


Regards

Jingyang, Teh



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JingyangTeh
Employee
824 Views

Hi


Any update on this case?


Regards

Jingyang, Teh


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JingyangTeh
Employee
791 Views

Hi


Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.



Regards

Jingyang, Teh


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