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Hi Community
I'm testing the I2C interface embedded in CycloneV - HPS.
- However, if I export peripherals signals through the HPS I/O Set everything works pretty well.
- But If I switch to FPGA: exporting signals to FPGA Fabric (integarting them with suitable I/O Tristate buffers) the I2C protocol is completely different, the frequency of I2C signals passes from 100kHx to 6 kHz, and even if SDA seems in a certain way coherent with data, SCL is not.
Please note the different behavior in the images attached.
Any help will be appreciated!
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Hi Stefano
Due to the year end festivals, a lot of my colleagues are on leave hence the slow response.
Sorry, I still got no update on this case as of now.
Regards
Jingyang, Teh
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Hi Stefano
There is an internal case number that was created to track this issue.( 15014617860 )
The engineering team will be taking a look at this. They will not be able to provide a patch anytime soon.
Is it okay if we close this case since that the HPS i2c Signal is okay when it is on the dedicated IO instead of through the FPGA fabric?
Regards
Jingyang, Teh
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Hi
Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.
Regards
Jingyang, Teh

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