Call module output - SystemVerilog

[antonto]

Hello,  I have a question and would be glad if somebody could help me, im a bit new to Systemverilog so bear with me! 

I have a project where i use two boards. First one is Intel DE10- lite and i have another board with M0 architecture. Basically i have to combine these two boards to work together. The m0 board has to send some data to the fpga where the fpga has to do some stuff and then send the data back to the m0 and the output of the fpga to be saved in a txt file. I have done this but with some more simpler stuff just to see it if works, for example a simple mux. So as the subject says I call some modules and i need the outputs of some modules to be returned to the top module and therefore to the m0 board. 


You will see from the pictures an output called loratest and this is the data that im sending to the other board. Now my question is how can i get the output symType from the module called loraPacketGenerator to the top module so i can send the data? 

[sstrell]

I'm assuming boardTest2.sv is the top-level of your design.  It's just a matter of instantiation and making the correct connections.  Where is loraPacketGenerator in your design hierarchy?  You show instantiations in img2.  Is the assumption these are in boardTest2?  If so, symType is already there as loraPacketGenerator_0_symval.  If you are saying it's lower down in the hierarchy, you just have to create an instantiation at the top that connects to the lower level module and signals.

[antonto]

Hello,  thank you for your time.

Im sorry but i didnt quite understand...This is my design hierarchy.

[SyafieqS]

Meaning that you just need to create a top module and port map to low level module and signal as per said

[antonto]

Hello, thank you for your time.

How do i do that? 

[SyafieqS]

Let me know if there is any update