Can I synthesize HDL, obtained as a result of DPC++ compilation, in Vivado for Xilinx FPGA?

[Vladislav-Butko-bvo]

I'm comparing two ways to get HDL from C++:
1) first, transform C++ to DPC++ and then apply icpx compiler;
2) using of Vivado HLS enviroment.

The comparison criteria of methods are some characteristics from the full compilation report in Vivado (for example, number of resources involved or delays on the paths).

But recently I found out that DPC++ is intended for Intel devices. And now I want to understand whether it makes sense to try to synthesize HDL, obtained as a result of DPC++ compilation, in Vivado for Xilinx FPGA, or is this obviously impossible or will it result in an extremely ineffective use of FPGA resources? Can the 1st method be winning according to any criterion?

[aikeu]

Hi Vladislav-Butko-bvo,

I think you can refer to the link below for further information:

https://www.intel.com/content/www/us/en/developer/tools/oneapi/dpc-compiler.html#gs.2w6w4u

Thanks.

Regards,

Aik Eu

[Vladislav-Butko-bvo]

I know that DPC++ allows, using a single syntax, to obtain cross-platform code targeting many devices with different architectures (for example, CPU, GPU, FPGA).

But my question concerned the possibility and feasibility of using DPC++ and oneAPI for programming Xilinx FPGA.

[Vladislav-Butko-bvo · Accepted solution]

I solved the issue myself. 

I cannot do comparasion of those HLS tool because those are under agreements what don't allow use output (HDL) of the tools of someone provider to programm FPGA another provider.

My short interpretation of Intel agreement: output files of icpx compiler can be used only for programming Intel FPGA.

Intel agreement cite: "Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors".
Source of Intel agreement: commentaries in first lines of HDL files obtained using icpx compiler on oneAPI platform.  

My short interpretation of Xilinx agreement: you cannot use Xilinx software to develop projects for devices other than Xilinx devices.

Xilinx agreement cite: "4. Restrictions. (a) Special Use Restrictions. No right is granted hereunder to use the Software or any Bitstream generated by use of the Software to program or develop designs for non-Xilinx Devices".
Source of Xilinx agreement: https://download.amd.com/docnav/documents/eula/end-user-license-agreement_2016.2.pdf.

Although, it's interesting that Vivado HLS output (HDL) can be used for succefull pragramming Intel FPGA. Source: https://support.xilinx.com/s/question/0D52E00006hpUOMSA2/transfer-the-hls-generated-veriloghdl-to-alteras-fpga?language=en_US.

[aikeu]

Hi Vladislav-Butko-bvo,

I think it is not feasible as there is no particular example which I can find to test that.

After consult the team, if trying oneAPI with other FPGA device (non-Intel), probably can go with the SYCL HLS flow (previously known as IP Authoring) where you can create IP using oneAPI environment to generate RTL model, then can further test with any simulation or systhesis tools for any prefered hardware.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Vladislav-Butko-bvo,

I will close this thread if not further question.

Thanks.

Regards,

Aik EU

[aikeu]

Hi Vladislav-Butko-bvo,

I am closing the thread for now. Feel free to open a new thread if there is further question.

Thanks.

Regards,

Aik EU