I have a design that has gone to production with a customer. The 10M08 device that I am using is 96% full, and the compilation time is quite reasonable for this percentage of logic use. My question is that in practicality can a Max10 device be made to be 100% full ?
You could probably come up with a design that is 100% utilized, but I would NEVER DO THAT. It basically gives you ZERO flexibility going forward. Even your 96% utilization is something I would never do, especially in a shippable product. Is your FPGA expected to be field upgradeable, or do you plan to offer new features in the future? What happens if you find a bug that needs to be fixed, and it causes your utilization to go from 96% to 101% (ie, it does not fit). Even at 90% utilization routing may not be possible and be able to meet timing constraints.
As general practice I would not recommend utilization above the 75% (typical) to 85% (maximum) range for a shipping product. If it is just a lab or hobby project then do whatever fits.
While I have been designing with FPGA's for 20 years, I have always adhered to the rule of no more than 50% FPGA device utilization when releasing a product to the field. Most large companies have a rule around this number.
However, this particular design has been tested extensively and I questioned the company as to whether there would be any future modifications. They answer is "NO" so the responsibility is on them for any issues that may arise with not having enough space.
However, in the process of doing the project, Quartus is able to synthesize the design to 96% full with ease, and this was a great surprise. The whole design synthesizes in less than 2 minutes. This prompts me to ask the question to Intel and the community at large about whether its even possible to fill the chip 100%.
This is an outlier case of fill percentage, so this is definitely not the norm, but still very worthwhile to understand the possibilities.
Hi James B,
When you have a larger design, the complexity is higher. A small or simpler design can achieve higher logic utilization compared to the larger design. If you use similar % of the logic utilization in the larger and complex design, you will easily see some fitter issue or timing issue.