Can sdram be accessed by multiple processors in Cyclone II FPGA?

[Altera_Forum]

Hello. I have a multiprocessor configuration set up in a Cyclone II device (EP2C35). I am currently using offchip sdram (Micron MT48LC4M32B2-7) for one processor and using on-chip RAM for the other...for all program memory, data memory, stack, etc. I am interested in adding another processor, but there is not enough on-chip RAM left. Is it possible to access the same sdram from multiple processors (but at different locations, naturally)? If so, how do I go about setting this up...should I use one SDRAM controller connected to each processor that needs it, or should I set up multiple controllers and somehow tell them to access different sections? Any advice is appreciated! Thanks!

[Altera_Forum]

This is really one of the nice features of SOPC builder: you just add your second, third...etc processor in SOPC builder and make sure it is connected properly (instruction or data or both depending on your software config) to the sdram controller already in place for your first processor. SOPC Bus fabric makes all the complicated arbitration and routing for you. Your challenge will be in software, to avoid conflicts in use of the data by sectioning the ram space, or use overlapping sections as mailboxes. So: One SDRAM controller only.  

 You may want to check out this thread: http://forum.niosforum.com/forum/index.php?showtopic=4580&st=0&gopid=24209&#entry24209 (http://forum.niosforum.com/forum/index.php?showtopic=4580&st=0&gopid=24209&#entry24209) Have fun.