The Board Test System (BTS) is able to detect the Stratix 10 FPGA.
When we set the the load selector switch (SW3.3) to ON and connect the board to the internet, the factory default design seems to be configured to the FPGA device. LEDs D1 and D8 are solid green. LEDs D4, D7, D9, and D10 are blinking between red and green. The board is able to receive an IP address, which is shown on the BTS GUI.
Following the instructions in Chapter 6.2 in the User Guide, we set the the load selector switch (SW3.3) to OFF and then try to use the BTS program to download other provided sample configuration files to the FPGA. These always fail.
Are you able to program the .sof file into the Stratix 10 using the Quartus programmer? Have you try to change the USB Blaster II TCK frequecy to lower frequency such as 16Mhz before programming the .sof?
Try to check on this.
We changed the frequency of the USB Blaster II TCK frequecy to either 16M or 6M using the following commands.
jtagconfig --setparam USB-blasterII[USB-1] JtagClock 6M
jtagconfig --setparam USB-blasterII[USB-1] JtagClock 16M
We used the following command to verify that the frequency was indeed changed to either 16M or 6M.
jtagconfig --getparam USB-blasterII[USB-1] JtagClock
After the frequency was lowered to either 16M or 6M, both Quartus Programmer and Board Test System (BTS) failed to configured the FPGA using the provided bitstreams.
BTW, I am using the Stratix 10 GX FPGA Development Kit.
Were you able to use the Qaurtus programmer to auto-detect the devices (S10 + MAX V) on the Stratix 10 dev kit? Which connector port on the Stratix 10 dev kit that you are using with the USB Blaster II? Please provide screen shot showing the auto-detect result. Can you provide screen shots on the Quartus programmer when trying to program the .sof file with the error message? Which Stratix 10 GX dev kit are you using? Is it the ES-L tile or ES-H tile or the Production-L tile board? You can only use the .sof file that matches with the board respectively.
I attached a couple of screen shots as the attached zip file.
0_KitTag: the tag of the kit. Based on the information, I assume it is ES-L tile board.
1_USB_Blaster: the port of the USB Blaster II.
2_AutoDetectorResult: The list of devices by the auto-detect.
3_AfterAddFile: After I added a provided bitstream file, say the bts_ddr4.sof under the 17.1/examples/board_test_system/image/LTES, a third device is added. The third device seems to be same to the detected device.
4_failed: I had to delete the detected S10 device (the middle one in 3_AfterAddFile.png) to configure. But the configuration failed very quickly.
5_detailedInfo: the output on the Quartus main console.
6_BTS_failed: the board test system also failed to configure the device.
bts_log: the log file generated by BTS.
The SWITCH 3.3 is OFF. All other dip switches follow the default settings on the user guide (page 10).
Thanks for the screen shot. Did you or Miaoqing Huang change the USB Blaster II TCK first to 16Mhz? Are you using the same Quartus version which is v17.1 since nedd to match with BTS v17.1 version? Before power up the dev kit, try to do this:
a) Disable the MAX V from the JTAG chain. Set the SW6.2 to ON to bypass the MAX V in the JTAG chain.
b) Then set the MSEL pins to JTAG mode only. You can set the MSEL pin at SW1 to 11.
Power up the board and set the USB Blaster II TCK to 16MHz or 6Mhz. Then perform auto-detect to make sure only Stratix 10 device is in the JTAG chain. Then try to program the bts_config.sof file.
Once we set MSL pins to JTAG mode only (SW1 to 11 based on user guide), we are able to configure the Stratix 10 device using the provided bitstreams.
It works under all three frequencies, i.e., 24MHz, 16 MHz, and 6 MHz.
If we disable the MAX V, we are able to configure the FPGA using the Quartus Programmer. If we enable the MAX V, we are able to configure the FPGA using both the Quartus Programmer and Board Test System.
Thanks for your help.
One more thing, if we insert the card to the PCIe port inside a computer, how to set SW1 to configure the FPGA properly? Do we need to change the setting of other DIP switches in the PCIe mode?
Miaoqing on behalf of David
Which configuration mode do you want use? JTAG or ASx4 or AVSTx16? You can still set the MSEL to JTAG or ASx4 or AVSTx16 to configure the Stratix 10 when power up. You just need to be careful on the power supply connection that need to be setup since you want to use PCIe application. Refer to chapter 3.1. Applying Power to the Development Board form the user guide. https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-fpga.html
Note: When operating as a PCIe add-in card, the board will not power on unless power is supplied to J26 and J27.