Clock Input voltage can be higher than VCCIO on Cyclone V devices?

[Zak]

Hello everyone,

I need to connect one 1.8V CMOS clock generator to a clock input pin of the IO bank I use for DDR3L (1.35V).

Since VCCPD=2.5V and VCCIO=1.35V on that bank, I'm not sure I can connect a 1.8V input, especially for clocking purpose.

Is it safe? If yes, does it have a bad influence on duty cycle and jitter of the clock signal? (different VIH and VIL I guess)

[YuanLi_S_Intel]

Hi Andrea,

I am assuming you are using differential SSTL-135 for DDR3L. The VCCIO used for this I/O Standard is 1.35V and VCCIO used for 1.8V LVCMOS is 1.8V. Thus it cannot be placed in the same bank. It would be better if you could place I/O standard of 1.8V on bank with VCCIO of 1.8V for stable signal integrity.

Thank You.

[Zak]

Yes, I know the VCCIOs are different, but I was wandering if maybe an INPUT only signal can be tolerated. 1.8V LVCMOS input with VCCIO=1.35V.

On the Cyclone V Datasheet there are no limits of input voltage associated to VCCIO. The only limitations are Vi>-0.5V and Vin<3.8V (p.5, Table 2).

[YuanLi_S_Intel]

Hi Andrea,

The limitation that you mentioned is meant for the IO buffer. If exceed that value, the IO buffer will be damaged.

So for the usage of 1.8V LVCMOS input on IO bank with VCCIO=1.35V, is not allowable in datasheet and we didnt test it before. So we cannot make any statement on that.

Thank You.