Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21595 ディスカッション

Clock Pin Input Requirements (Crystal OK? MAX10 specifically)

Altera_Forum
名誉コントリビューター II
2,315件の閲覧回数

Hello all, 

 

Is it possible to use a crystal as the external clock source instead of an oscillator? I'm building a design based off the MAX10, and the evaluation board uses the CB3LV-3C-50M0000 50MHz crystal oscillator. My goal is to reduce the overall power consumption though, so I'm curious, can I connect a crystal to the clock port instead. 

 

I've searched through the Altera MAX10 datasheet, clock and PLL user guide, and pinout specifications to no avail.  

 

Thanks for your time and insight! 

J
0 件の賞賛
3 返答(返信)
Altera_Forum
名誉コントリビューター II
1,396件の閲覧回数

Simple answer is no, not possible. The clock inputs are all logic level inputs. Driving / receiving a discrete crystal requires special I/O circuitry which is not present. 

 

Theoretically you could put a power switch on your oscillator to turn it off when you are not using it (ie, in some kind of sleep mode) but in the overall scheme of things the power dissipation of the oscillator is minimal compared to that of the MAX10 FPGA.
Altera_Forum
名誉コントリビューター II
1,396件の閲覧回数

Thanks for the reply, ak6dn! 

 

For future reference, do you know if any of this information is available in Altera's documentation?
Altera_Forum
名誉コントリビューター II
1,395件の閲覧回数

You find some hints about clock inputs in the "MAX 10 FPGA Signal Integrity Design Guidelines". Simultaneous switching noise (SSN) is a sufficient reason why a built-in crystal oscillator would be a bad idea.

返信