Clock Pins in Cyclone V

[Altera_Forum]

Hello, 

 If I want to connect HSMA_CLK_IN_P2/N2 (which refers to CLK7p/n on my 5CSXFC6D6F31C8NES) to a PLL, I have to place the PLL in one of the two quadrants on the right of the chip, am I right? By using CLK7n as single ended clock, I could avoid this?  Thanks

[Altera_Forum]

From the 'Clock Network Sources', page 4-7: 

http://www.altera.com/literature/hb/cyclone-v/cv_52004.pdf (http://www.altera.com/literature/hb/cyclone-v/cv_52004.pdf)    --- Quote Start ---  The CLK<#>n pins drive the PLLs over global or regional clock networks and do not have dedicated routing paths to the PLLs.  --- Quote End ---    If the dedicated clock pins can drive the PLLs via the global clock networks this suggests there are no restrictions as to which PLLs can be driven from any dedicated clock inputs. However, the document goes on to discuss jitter if the global or regional clock resources are used along with Altera's recommendations regarding the use of PLLs. Depending on your requirements selecting a PLL away from the edge with the dedicated clock input may or may not be appropriate.  As for using a single ended clock - no, this won't gain you anything. The physical layer clock signal (differential or single ended) is terminated in the IO cell, before being driven onto a clock network. Driving a single ended clock in won't help with internal routing or choice of PLL.

[Altera_Forum]

Thank you. That is exactly the text I read and, obviously, misunderstood. 

Why cannot I use each clock input in conjunction with the hardware SERDES and a fractional PLL placed at X0Y74? The fitter always complains.  Is there a way to solve this issue? For PLLs, an altclkctrl block is said to solve this, but this does not work with the serdes.

[Altera_Forum]

I don't understand what you're trying to do. How many clock inputs are you trying to feed to the PLL at the location you specify? Why must you place the location you specify?

[Altera_Forum]

I am trying to use two serdes with an external PLL and to connect them to the HSMC connector. 

As I want to receive the tx-clock from the opposite side and also to send the tx-clock of my side, Quartus constrains the PLL's location to X0 Y74, otherwise it refuses to place the PLL. That is a problem as I want to configure the PLL to be able to switch between a clock on my board (not the tx-clock but an external clock) and the received clock (the tx-clock of the other side). I have still not managed to route one of the clock sources on the Cyclone V SoC Dev Board to this location.

[Altera_Forum]

--- Quote Start ---   I want to configure the PLL to be able to switch between a clock on my board ... and the received clock   --- Quote End ---   Are you trying to do this in a single FPGA image? Quartus is not going to let you select between two (or more) clocks to feed a single PLL.  You can either: 1) Use an extenal loop - assuming you have one or can add one. Select and feed your clock out on the external loop, back into a dedicated clock pin that feeds the PLL. However, a word of warning, this will only add jitter. If you have tight jitter requirements this probably won't do.  2) Reprogram the FPGA with a different image designed to drive the same PLL from a different clock source. This is clearly dependant on your hardware supporting such a scheme. Cyclone V supports multiple images from a single boot device. If this is purely a 'lab' based project (rather than a product) then this is somewhat easier.  Cheers, Alex