Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21616 Discussions

Clocking of transceiver in CIV GX

Altera_Forum
Honored Contributor II
‎06-07-2012 05:34 PM
1,253 Views

Hello everyone! 

 

I want to use LVPECL clock generator for REFCLK input of transceiver. 

According to CIV Handbook, it is necessary to use AC coupling. 

Also there is the drawing of clocking scheme (see Fig.1-27 of CIV Handbook, Volume 2) with external termination on REFCLK inputs. 

 

Is there internal termination on the REFCLK inputs for clock input, similar to internal termination on GXB_Rx inputs of transceiver ? 

If so, can I use internal termination on REFCLK inputs instead of external termination ? 

 

Thanks.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎06-07-2012 07:52 PM
540 Views

See table 6-10: Termination has to be off chip. There is no internal termation at all on clock inputs (nor on any other IO as far as I know).

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.