Clocking of transceiver in CIV GX

[Altera_Forum]

Hello everyone! 

 I want to use LVPECL clock generator for REFCLK input of transceiver. According to CIV Handbook, it is necessary to use AC coupling. Also there is the drawing of clocking scheme (see Fig.1-27 of CIV Handbook, Volume 2) with external termination on REFCLK inputs.  Is there internal termination on the REFCLK inputs for clock input, similar to internal termination on GXB_Rx inputs of transceiver ? If so, can I use internal termination on REFCLK inputs instead of external termination ?  Thanks.

[Altera_Forum]

See table 6-10: Termination has to be off chip. There is no internal termation at all on clock inputs (nor on any other IO as far as I know).