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Combine PCIE and SGMIIs in QSYS structure Cyclone V

Majo
Beginner
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Hi,

I use PCIE HIP in Cyclone V wrapped into QSYS structure. Is it possible to add multiple (3 ports) of TRI Ethernet (SGMII) IPs to this existed PCIE QSYS structure? I have succeeded to add only 1 port while adding additional 2 ports I have an error  Error (175001): The Fitter cannot place 1 HSSI PMA Aux...

I know how to implement these 3 ports separately from the QSYS wrapper using a common fractional pll for TX transceiver cannels. But in TRI IP core I see an option xN in TX PLL clock network that I assume is similar when using a separate common fractional pll. But it also doesn't work.

 

Thanks for all tipping. 

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wchiah
Employee
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Hi


Please refer to the C5 Transceiver datasheet , the PCIe x1 will take up 2 channel for the placement , this is the limitation for the device itself , this means only one PCIe and one SGMII is possible for your solution , thanks 

 


Regards,

Wincent_Intel


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Majo
Beginner
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Hi wchiah,

Thanks for the response. In my previous message I wasn't full. My Cyclone V device has 6 trans (2 blocks with 3 transceivers). The PCIE HIP occupies 2 trans as a result there are 4 unoccupied trans. 

I can compile the project there I have 1 PCIE wrapped into QSYS and 3 SGMIIs separate from QSYS as Native PHY IPs. I am trying to understand that it is impossible to have in one QSYS structure 1 PCIE and 3 SGMII as TSE (Triple-Speed Ethernet) IPs instead of 3 SGMII Native PHY IPs.

 

BR, Majo

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wchiah
Employee
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Hi,


The error code state that the reconfiguration controller is removed. This note ties in with the error message which suggests a problem with the PMA_AUX block.

 

The PMA_AUX block is a physical circuit inside the FPGA that the reconfiguration controller IP must access. For your design to fit, all transceivers must connect to a reconfiguration controller.

 

One other possibility I can think of here is that you’ve used the PCI Express Design example in your project. It has been a while since I have looked at this design on Cyclone V but I seem to remember that the design example instantiates the reconfiguration controller within the IP. IF you have two reconfiguration controllers trying to access the same transceiver block then this might cause a connection conflict. There is more information about connecting the reconfiguration controller in the V-Series PHY IP userguide.

 

The chapter name is “Transceiver Reconfiguration Controller to PHY IP Connectivity”

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf

 

I believe you might be violating figure 17-13.

 

IF you are using the PCI Express design example, you might need to remove the reconfiguration controller and instantiate a single one outside of the IP that connects to PCI Express blocks.


Regards,

Wincent_Intel


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Majo
Beginner
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Hi Wincent,

 

Thank you for your assistance. I could compile one PCIE and couple SGMII interfaces in one QSYS project when I set the common reference clock 125 MHz for all transceivers. I believe that combination helps to use a common TX PLL for all transceivers. 

 

BR, Majo

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wchiah
Employee
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Hi Majo,

 

Glad that you found the solution, Also thanks for sharing with me how you solve it.

Therefore following our support policy, I have to put this case in close status and this thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

 

Regards,

Wincent_Intel


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