Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20875 Discussions

Timing violations while integrating 2 display port example designs..

paul26
Beginner
605 Views

Hi,

I have generated an example design for display port which compiled successfully. As we are dealing with 2 display ports i made a second instantiation of the same example top. this time i got a timing violation in the following path, which I could not solve. But the project is working fine when I test in the board. Can you please help me to solve this timing violation?

 

Here is the details of timing violation

paul26_0-1688387571266.png

 

ex:

 

Critical Warning: Unexpected timed setup path
From: top_dp|tx_phy_top_i|gxb_tx_i|gxb_tx|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_pldadapt_tx.inst_ct1_hssi_pldadapt_tx|pld_pcs_tx_clk_out2_dcm
To: top_dp2|tx_phy_top_i|gxb_tx_i|gxb_tx|g_xcvr_native_insts[0].ct2_xcvr_native_inst|inst_ct2_xcvr_channel_multi|gen_rev.ct2_xcvr_channel_inst|gen_ct1_hssi_pldadapt_tx.inst_ct1_hssi_pldadapt_tx~pld_tx_clk2_dcm.reg
Source Clock: top_dp|tx_phy_top_i|gxb_tx_i|tx_clkout2|ch0
Destination Clock: top_dp2|tx_phy_top_i|gxb_tx_i|tx_clkout2|ch0

 

paul26_1-1688387571615.png

 

component instantiation. 

refclk1 is 100MHz

xcvr_refclk is 135Mhz

Labels (1)
0 Kudos
3 Replies
RichardTanSY_Intel
570 Views

There is a possibility that the timing violation you are seeing could be a false path.

You need to review and check whether the timing path mentioned in the violation is relevant to the circuit's operation.

If you believe it is a false path, you can use the 'set_false_path' command to exclude that specific path from the timing analysis.


By the way, I noticed that you have posted two similar cases, one here (link: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Timing-violation-while-integrating-2-display-port-example/m-p/1501202#M79114) and another one here.

Please note that it is not recommended to file duplicate cases, and we do not provide support for duplicated cases.

I will transition this thread to community support, while your other case will be handled by one of my colleagues.


If you have any further questions or concerns, please don't hesitate to reach out.

Thank you, and have a great day!


Best Regards,

Richard Tan


p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 



0 Kudos
paul26
Beginner
567 Views

Hi, 

i used false path command in that specific path, even that didn't solve the problem.

0 Kudos
RichardTanSY_Intel
541 Views

When you report timing the failing slack, in the timing report, you can right-click the failing path, Set False Path(between nodes or clock). In this case, this seem to be clock-to-data analysis.

Select Set False Path (between clock) > Update Timing Netlist > Setup Summary. You will see the first timing violation has gone. Repeat the rest of the timing path violation (make sure to check whether the timing path can be false path.)

capture.JPG

Best Regards,

Richard Tan

 

0 Kudos
Reply