I need to implement a communication between two FPGAs, one Cyclone V and one Cyclone 10 LP. Both devices will be connected using a fiber cable, so I have one tx and one rx lane.
Because of the Cyclone 10 LP missing a Gxb transceiver, I thought about using the altlvds ip + external pll for rx and an external 8b/10b coding, for the communication.
Could this setup do the job? Is it possible to adjust the pll using dynamic phase shift / reconfiguration for reliable data transfer?
The first problem I face with the idea above starts with the fitter for some reason I’m not able to implement this setup on the Cyclone V. Fitter throws error:
Error (11239): Location FRACTIONALPLL_X0_Y1_N0 is already occupied by pll_tx:pll_tx0|pll_tx_0002:pll_tx_inst|altera_pll:altera_pll_i|general.gpll~FRACTIONAL_PLL.
Even though I only use 2 of 6 plls in this design.
So could you please tell me if this idea is completely off, and/or if there is a better way to do it?
I suppose my main issue will be the clock recovery, I’m still not sure myself on how I should do this, using the setup above.
Or would a slower communication (using oversampling) be a better/easier solution?
Because many control signal will be transmitted, the communication should feature a low latency, while the actual bandwidth doesn’t need to be that high. (We will transmit data chunks of about a few bits).