Hi Altera Experts,I've purchased a DE0-Nano Development Board and am attempting to compile the first example: https://www.physics.wisc.edu/undergrads/courses/fall2014/623/altera-deo_reference/de0-nano_my_first_... The compilation has stalled at 83%. It is unclear, but it seems to be due to 'Unconstrained Paths' within the TimeQuest Timing Analyzer. The relevant log messages should be these: Warning (332087): The master clock for this clock assignment could not be derived. Clock: inst1|altpll_component|auto_generated|pll1|clk was not created. Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk Warning (332060): Node: CLOCK_5 was determined to be a clock but was found without an associated clock assignment. Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. Warning (332056): PLL cross checking found inconsistent PLL clock settings: Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 Warning (332061): Virtual clock CLOCK_5 is never referenced in any input or output delay assignment. Given that I am a complete beginner attempting my first example, can you please describe clearly how I can debug this? Are there further files that I should attach? Many Thanks, Will http://www.alteraforum.com/forum/attachment.php?attachmentid=13046&stc=1
What operating system are you running on your computer?What version of Quartus have you installed? Where did you get your demo software? Did you download it from the TerAsic suite, or is it from an included CD?
Hi ak6dn,--- Quote Start --- What operating system are you running on your computer? What version of Quartus have you installed? Where did you get your demo software? Did you download it from the TerAsic suite, or is it from an included CD? --- Quote End --- Windows 10, 64-bit Quartus II 13.0 (64-bit) It is from the DE0-Nano included CD Thanks, Will
Per Altera's wbsite, the following are Quartus system requirements:
HiDespite the OS compatibility issues, try a simple example first. A counter is a good starting point and see if it works. Then do a complex synthesis. Sometimes the synthesis process may last for hours depending on the design and FPGA capabilities. The TimeQuest warnings normally do not result in such situations.
--- Quote Start --- if there is a way I can improve my post to better allow for expert help --- Quote End --- Provide readable pictures in your post. Missing timing constraints or timing violation will usually not prevent design compilation. Please also tell what's the "first example" you tried to compile (design name).