Complex dual tone generation

[Altera_Forum]

Hello, 

 I am trying to realize a VHDL code able to generate a complex baseband dual tone signal. What i would like to to is then send this signal through the HSMC port to a DAC evaluation board, where the DAC is reconstructing the analog signal. I have started my design in this way, I basically use a PLL in order to generate the clock for two different NCO Megacore functions (configured to oscillate at two different frequencies with CORDIC implementation, and to send in output both sine and cosine signals). After that I sum the two I components, and Q components together using a 16 bit adder block.  After this I have connected an IO_LVDS_BUFFER making the signal differential to connect it to the LVDS transmitter on the HSMC port, ready to be sent to the DAC.  Here I am completely leaving apart the fact that I should interleave the I and Q components, as the dac would like.........  Is there somewhere a nice example to start with, for the realization of a complex dual tone sinusoidal signal?  Greetings,   Giovanni

[Altera_Forum]

--- Quote Start ---  Hello,  I am trying to realize a VHDL code able to generate a complex baseband dual tone signal. What i would like to to is then send this signal through the HSMC port to a DAC evaluation board, where the DAC is reconstructing the analog signal. I have started my design in this way, I basically use a PLL in order to generate the clock for two different NCO Megacore functions (configured to oscillate at two different frequencies with CORDIC implementation, and to send in output both sine and cosine signals). After that I sum the two I components, and Q components together using a 16 bit adder block.  After this I have connected an IO_LVDS_BUFFER making the signal differential to connect it to the LVDS transmitter on the HSMC port, ready to be sent to the DAC.  Here I am completely leaving apart the fact that I should interleave the I and Q components, as the dac would like.........  Is there somewhere a nice example to start with, for the realization of a complex dual tone sinusoidal signal?  Greetings,   Giovanni  --- Quote End ---    I believe you have already described your own nice example . What is your difficulty?

[Altera_Forum]

--- Quote Start ---  I believe you have already described your own nice example . What is your difficulty?  --- Quote End ---    Hello kaz!  Thank you for your answer. Basically my design example is convincing me too now, but I was just thinking if there are other ways in order to implement my dual tone, maybe I could even save a signal on the DDR3 memory, and replay it over the HSMC connector? Or other ways? Are there somewhere other design examples?   Best regards,   Giovanni.

[Altera_Forum]

--- Quote Start ---  Hello kaz!  Thank you for your answer. Basically my design example is convincing me too now, but I was just thinking if there are other ways in order to implement my dual tone, maybe I could even save a signal on the DDR3 memory, and replay it over the HSMC connector? Or other ways? Are there somewhere other design examples?   Best regards,   Giovanni.  --- Quote End ---    Yes the simplest way is to have a precomputed fixed vector stored in fpga rom then read it out. You can then vary the read rate to get various values of your dual tone. In effect an LUT. You can also vary your scaling. But be careful about phase continuity at end of your vector with its start.

[Altera_Forum]

Hi Kaz,  

 thanks for your replies, I have found another point during the development of my testing system which is not really cleart to me. I have implemented my system as I have described at the beginning of this post, but now I have a small problem interfacing my design with my DAC evaluation module. I don't know if I am doing right on the FPGA side, but basically I want now to play my signal on the HSMC connector by sending the data and the data clock for the evaluation board. The point is that the generated signal is in baseband, but in order to feed it inside the DAC board, I need to interleave it. Basically the DAC will accept interleaved LVDS data, I have 16 bits out of my VCO for the sine and cosine components. After the NCO megacore block, I use a multiplexer to implement the data interleave (basically my idea is that when the clock is on the rising edge, I send a 16 bits sample for the sine component and when there is a falling edge I send a sample from the quadrature component).  Now, which one would be the best way to interface this to my DAC evaluation module? At the beginning I just went to the pin planner, and I have configured each HSMC TX pin as LVDS, then I routed the output of the multiplexer just to the positive pins. As I have read around on the forum, quartus should generate the differential pair automatically....  But...does this mean that I am done when I do so? Or should I use a ALTLVDS_TX megacore after the multiplexer?  The problem is that at the moment I don't have a real way to test if I am actually sending something to the HSMC pins, but would be nice to understand if at least operatively I am doing right.  DO you have any suggestion for me?

[Altera_Forum]

--- Quote Start ---  Hi Kaz,   thanks for your replies, I have found another point during the development of my testing system which is not really cleart to me. I have implemented my system as I have described at the beginning of this post, but now I have a small problem interfacing my design with my DAC evaluation module. I don't know if I am doing right on the FPGA side, but basically I want now to play my signal on the HSMC connector by sending the data and the data clock for the evaluation board. The point is that the generated signal is in baseband, but in order to feed it inside the DAC board, I need to interleave it. Basically the DAC will accept interleaved LVDS data, I have 16 bits out of my VCO for the sine and cosine components. After the NCO megacore block, I use a multiplexer to implement the data interleave (basically my idea is that when the clock is on the rising edge, I send a 16 bits sample for the sine component and when there is a falling edge I send a sample from the quadrature component).  Now, which one would be the best way to interface this to my DAC evaluation module? At the beginning I just went to the pin planner, and I have configured each HSMC TX pin as LVDS, then I routed the output of the multiplexer just to the positive pins. As I have read around on the forum, quartus should generate the differential pair automatically....  But...does this mean that I am done when I do so? Or should I use a ALTLVDS_TX megacore after the multiplexer?  The problem is that at the moment I don't have a real way to test if I am actually sending something to the HSMC pins, but would be nice to understand if at least operatively I am doing right.  DO you have any suggestion for me?  --- Quote End ---    Once you get your interleaved stream(SDR on rising edge only) you then pass it through altddio_out which will convert it to DDR (rising/falling edges) Then you pass it to the pins (you can directly connect to positive pins only or use altlvds). These are two separate steps so don't mix up between them.

[Altera_Forum]

Hi Kaz, 

 I have tried to simulate the sample interleaving thorugh a multiplexer. In order to test if this interleaving is working, I have set up a test bench: I have two 16 bits counters, driven by a clock signal with 10 ns of period. After this I have my MUX, where the select signal is driven by the same clock which I am using to trigger the counters. When I simulate this, I see that on each rising edge of the clock, the counters are counting correctly, but the output of my system is just changing with every rising edge of the clock. Normally I would expect that the output of my MUX may change when the selector signal has a logic value of 0., in such a way that during a clock cylce I sent out of my mux two different data in a row. Am I facing a timing constraint? Such as, my data will really take not less that one clock cycle even if I play around with the select signal of the following MUX?

[Altera_Forum]

--- Quote Start ---  Hi Kaz,  I have tried to simulate the sample interleaving thorugh a multiplexer. In order to test if this interleaving is working, I have set up a test bench: I have two 16 bits counters, driven by a clock signal with 10 ns of period. After this I have my MUX, where the select signal is driven by the same clock which I am using to trigger the counters. When I simulate this, I see that on each rising edge of the clock, the counters are counting correctly, but the output of my system is just changing with every rising edge of the clock. Normally I would expect that the output of my MUX may change when the selector signal has a logic value of 0., in such a way that during a clock cylce I sent out of my mux two different data in a row. Am I facing a timing constraint? Such as, my data will really take not less that one clock cycle even if I play around with the select signal of the following MUX?  --- Quote End ---    Your edge interleaver(DDR) can be done readily using altddrio_out. There is no reason to design your own unless you know what you are doing. You pass cos data and sin data in parallel into altddrio_out together with their clock and you are done.

[Altera_Forum]

--- Quote Start ---  Your edge interleaver(DDR) can be done readily using altddrio_out. There is no reason to design your own unless you know what you are doing. You pass cos data and sin data in parallel into altddrio_out together with their clock and you are done.  --- Quote End ---    Hi Kaz,  I have tested the altddio_out megacore on my design but I have still a problem in getting it to work as expected. I have had a look into the megacore manual, and I saw that this block would do exactly what I would like to do, but when I simulate it in Model-Sim I just cannot see the DDR behavior.  Basically I have two counters in my testbench, counting with the same clock period, so once they pass throught the altddio_out block, I should see in output a dual data rate signal, but this seems not happening. What could it depend on? I will try to follow a basic tutorial on the altddio_out megacore, but I think I´m using the block correctly.

[Altera_Forum]

--- Quote Start ---  Hi Kaz,  I have tested the altddio_out megacore on my design but I have still a problem in getting it to work as expected. I have had a look into the megacore manual, and I saw that this block would do exactly what I would like to do, but when I simulate it in Model-Sim I just cannot see the DDR behavior.  Basically I have two counters in my testbench, counting with the same clock period, so once they pass throught the altddio_out block, I should see in output a dual data rate signal, but this seems not happening. What could it depend on? I will try to follow a basic tutorial on the altddio_out megacore, but I think I´m using the block correctly.  --- Quote End ---    make one counter start from 0 and increment by 2 (0,2,4,...) set other counter to start at 1 and increment by 2(1,3,5...) then the ddr output should be 0,1,2,3,4... assuming you feed the pair in that sense

[Altera_Forum]

--- Quote Start ---  make one counter start from 0 and increment by 2 (0,2,4,...) set other counter to start at 1 and increment by 2(1,3,5...) then the ddr output should be 0,1,2,3,4... assuming you feed the pair in that sense  --- Quote End ---    Hi Kaz,  I have managed to simulate that, and I have found out that this is possibly just the way Model-Sim represents the data. I have made the second counter start from 5000 and the first from 0. When I run the simulation now I see clearly that the signals are switching with double data rate, so if the data I am interleaving are exactly the same, it´s basically always like having a single data rate, and Model-Sim doesn´t represent the signal´s switching, and this makes sense....  Thanks for your help!