- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I have a question about the configuration of a Cyclon IV with a EPCS in AS mode. The problem is, that I use the LVDS ports of bank 1/2, so I have to supply these banks with 2.5V. The configuration pins are also on the first bank. The configuration device EPCS must be supplied with 3.3V. So the I/O voltage of the configuration device is about Vs-0.3V. The question: Is it possible to connect the configuration pins of FPGA and EPCS, without any protection? (The internal clamp diode is not availible for the configuration pins)Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Altera suggests a series resistor at EPCS data ouput to reduce overshoots. There will be no problems when driving a 2.5V bank from 3.3V logic, as long as no severe overshoots are generated. According to specified in- and output levels, the problem is in driving a 3.3V CMOS device with a 2.5 V I/O standard. See the I/O standard matrix in Cyclone IV device manual.
See this recent discussion http://www.alteraforum.com/forum/showthread.php?t=31810- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you, for the fast response.

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page