Cyclone 'EP1C3T100C8N' schematics

[Altera_Forum]

I have searched high and low and just cant find a simple schematic (bare minimum) to get this chip up and runnning. 

 Im just after how you wire it up with a JTAG interface and a simple boot prom.  Any idea where i can find this?  Thank you

[Altera_Forum]

--- Quote Start ---  I have searched high and low and just cant find a simple schematic (bare minimum) to get this chip up and runnning.  Im just after how you wire it up with a JTAG interface and a simple boot prom.  Any idea where i can find this?   --- Quote End ---    Have you read the device handbook?  http://www.altera.com/literature/lit-cyc.jsp  Generally, you need to power up the core voltage and each of the I/O banks within a specified time, configure the JTAG interface with appropriate pull-ups or downs on the signals (so they do not float when the USB-Blaster is not present), and wire up the EEPROM.  For example designs, just look at the schematics for a reference board. Don't worry if you cannot find an EP1C board, look for a Cyclone II or III, the JTAG and EEPROM interfaces have not changed.  Cheers, Dave

[Altera_Forum]

I see, iv attactched the schematic of the development board im using. but i would like to use a EP1C3T100C8N in my actual design not the EP2C5T144C8 

 So the JTAG and boot prom connections will be identical on the EP1C3T100C8N, its just a matter of using this chip and wiring it up the same as the EP2C5T144C8   Im a bit scared of forgetting to GND some special pin or having to have one held high  Thanks :)

[Altera_Forum]

--- Quote Start ---  I see, iv attactched the schematic of the development board im using. but i would like to use a EP1C3T100C8N in my actual design not the EP2C5T144C8  So the JTAG and boot prom connections will be identical on the EP1C3T100C8N, its just a matter of using this chip and wiring it up the same as the EP2C5T144C8  Im a bit scared of forgetting to GND some special pin or having to have one held high   --- Quote End ---    The schematic looks fine.  If I don't have a processor implementing the programming interface, then I like to put LEDs on signals, eg. the STATUS# signal will go low when there is a problem, so you can put a red LED on that and the CONF_DONE signal goes high when the FPGA is configured, so you can either use a red LED to indicate not configured, or a green LED to indicate its configured (I generally use a TinyLogic to drive LEDs; sink or source depending on when you want the LED on).  Here's a reference schematic and some other docs:  http://www.ovro.caltech.edu/~dwh/carma_board/ http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_rev_a.pdf  Cheers, Dave

[Altera_Forum]

Thanks :) 

 Just checked the schematic part, I cant beleave how simple these things are to setup :)

[Altera_Forum]

--- Quote Start ---   Just checked the schematic part, I cant beleave how simple these things are to setup :)  --- Quote End ---  Still, people do get it wrong ... as recent threads show. Here's few warnings;  1) Connection all VCCIO power banks, even if you do not use pins on those banks.  2) If the package has a power-pad (underneath it), make sure to connect it.  3) Connect all the device-specific programming pins appropriately, eg., nCE, MSEL[], nCONFIG, nSTATUS, CONF_DONE, (optional INIT_DONE), etc.  4) Connect the JTAG interface. Use a shrouded header for the PCB layout, as it helps to get the cable orientation correct. Make sure you leave enough room around the part.  5) Include a power-on-reset supervisor IC external to the FPGA. Its nice for producing a nice clean reset signal. You can usually connect a push-button input into the reset supervisor IC, and it'll debounce the signal for you.  Look at other peoples designs, try to understand them.  Cheers, Dave

[Altera_Forum]

Thanks :) 

 Ill make sure to upload my schematic once complete :)