Constraints for inverted clocks

[Altera_Forum]

The task looks simple, but I don’t know which constrain to use. 

I have to output two signals (200 MHz clocks) from FPGA. First is an inversion of the second:   Mem_ClkP <= Clk; Mem_ClkN <= not Clk;  How to tell fitter and timequest, that these signals should arrive at external memory with phase = 180 +/- 5 degrees (5 – just for example)? Assume, that FPGA-Memory traces for both signals are equal.  Thank you.

[Altera_Forum]

I wouldnt do that. The fitter will struggle to get any phase relationship between the two as the phase will be dependent on the routing of Mem_ClkN. What you need is both to be the output of a PLL, with a specified phase relationship.

[Altera_Forum]

Thanks for quick reply. 

Actually, my question is not about real project. I am just learning constraints.  Pll is a good thing, but if FPGA does not have it? (Acex, for example).

[Altera_Forum]

You can also try ddr outputs to generate clocks (instead of data, you output '0' then '1' for one clock, '1' and '0' for the other) and apply constraints on ddr io

[Altera_Forum]

If you're using an Acex, you wont be using a 200MHz clock, or constraints....

[Altera_Forum]

Thank you. 

But I am not designing a real device. I'm just learning constraints. Everything you suggest will work, of course, but I want to play with timequest and fitter, setting different phase deviations.  If there is no such constraint, I`ll stop thinking about that.