Re: Cpld max v - i2s

Altera_Forum · ‎07-18-2018

hello everybody

I'am a beginner at the VHDL programming. I use CPLD Max V (5M570ZF256C5N) in my internship and I have to write a program in VHDL. the program is selection between two audio sources via I2S bus. so I do not know how to write the I2S protocol on quartus

can you help me to solve this problem.

thank you.

Altera_Forum · ‎07-19-2018

Hi,

1. Collect information about HDL (VHDL, Verilog) languages & I2S protocol like IEEE Papers, Case study, Thesis etc.

2. Study & understand the protocol.

3. Start HDL coding parallel & also go through the Intel online training for HDL & Quartus tool.

Refer the following links & attachment,

https://www.altera.com/support/training/curricula.html

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎07-19-2018

thank you Mr vikas

Altera_Forum · ‎07-19-2018

hello vikas

i have read the PDF tha you give me and i searched on the internet. I found the I2S_interface VHDL program. i tried to compile it but I had some error. after resolve the maximum possible of error I still have some of them.

here is the message that says there is an error:

here is the code :

Altera_Forum · ‎07-20-2018

Hi,

generic ( DATA_WIDTH : integer range 16 to 32;
                             BITPERFRAME : integer );
Modify the code like bellow,
generic ( DATA_WIDTH : integer := 32;
                BITPERFRAME : integer := 0
              );
If want to use in the range format then use a signal like a bellow,
signal temp : integer range 0 to DATA_WIDTH := 0;

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎07-23-2018

hello Mr Vikas

I complited the program successfully without error and I did a simulation but I received this result. I think there is a problem.

imad bourja

Altera_Forum · ‎07-23-2018

Hi,

The screenshot is not visible properly.

Have you provided all input stimulus in Testbench? If not then refer testbench format from Google & check again.

Please open a new thread for better support.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎07-23-2018

I also found the testbensh of this code.

Altera_Forum · ‎07-23-2018

hello vikas

I simulated the test bench in RTL STIMULUS and I received these results.

I think there is an error in the adc signal.

imad bourja

Altera_Forum · ‎07-25-2018

hello Mr vikas,

finally I had the satisfactory result about I2S. I am based on the documents that you gave me.

this is the simulation on ModelSim.

thank you again .

imad,