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On my design i have 2 processor, and i need to make for every one 2 pin( 1 input and one output). And relate the output for CPU1 with input for CPU2, also the iput from the CPU 1 with output from CPU2.
My problem how can i relate with these pin as i mentionned.Link Copied
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I presume your processors are Nios, then you can easily do it with PIOs.
One processor drives a PIO output which is connected to a PIO input (and possibly an IRQ) on the other processor. Same for signaling in the opposite direction. This requires you connect PIOs externally to your sopc/Qsys module. I think you could also make everything inside the module, if your cpu1 directly asserts the irq signal for irq2 and viceversa, but I don't know if this is easy to implement: probably you need to define a custom component which is capable to assert irqs.- Mark as New
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If you instantiate the system in a schematic, connect outputs to inputs with a wire. If you instantiate in HDL, write the assignement code for PIO port signals.
I was thinking now that probably you can make everything inside sopc system, using only two PIOs, bidirectional, 1 bit wide. Each PIO is written by one cpu (as output) and read (as input and/or IRQ) by the other cpu. You have to try; I've never done something like this, so I'm not sure it iwill work.- Mark as New
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--- Quote Start --- If you instantiate the system in a schematic, connect outputs to inputs with a wire. If you instantiate in HDL, write the assignement code for PIO port signals. --- Quote End --- Ok i will try to release it but can you give me an example code assignement, because whem i try to assigne the output and input to the same pin assignement, there are a code error that isn't possible to connect two pin the same pin assignement.
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Verilog:
wire signal_cpu2_to_cpu1;
wire signal_cpu1_to_cpu2;
Nios_system inst1(
.clk(your_clock),
.reset_n(your_reset),
....
.in_port_to_the_cpu1_pio_in(signal_cpu2_to_cpu1),
.in_port_to_the_cpu2_pio_in(signal_cpu1_to_cpu2),
.out_port_from_the_cpu1_pio_out(signal_cpu1_to_cpu2),
.out_port_from_the_cpu2_pio_out(signal_cpu2_to_cpu1),
.... );
VHDL: SIGNAL signal_cpu1_to_cpu2 : STD_LOGIC;
SIGNAL signal_cpu2_to_cpu1 : STD_LOGIC;
COMPONENT Nios_system
PORT (
clk : IN std_logic;
reset_n : IN std_logic;
....
in_port_to_the_cpu1_pio_in : IN std_logic;
in_port_to_the_cpu2_pio_in : IN std_logic;
out_port_from_the_cpu1_pio_out : OUT std_logic;
out_port_from_the_cpu2_pio_out : OUT std_logic;
.... );
END COMPONENT;
inst1 : Nios_system
PORT MAP (
clk >= your_clk,
reset_n >= your_reset,
....
in_port_to_the_cpu1_pio_in >= signal_cpu2_to_cpu1;
in_port_to_the_cpu2_pio_in >= signal_cpu1_to_cpu2;
out_port_from_the_cpu1_pio_out >= signal_cpu1_to_cpu2;
out_port_from_the_cpu2_pio_out >= signal_cpu2_to_cpu1;
);
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Thank you very much.
Now i will try to implement.- Mark as New
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--- Quote Start --- Verilog:
wire signal_cpu2_to_cpu1;
wire signal_cpu1_to_cpu2;
Nios_system inst1(
.clk(your_clock),
.reset_n(your_reset),
....
.in_port_to_the_cpu1_pio_in(signal_cpu2_to_cpu1),
.in_port_to_the_cpu2_pio_in(signal_cpu1_to_cpu2),
.out_port_from_the_cpu1_pio_out(signal_cpu1_to_cpu2),
.out_port_from_the_cpu2_pio_out(signal_cpu2_to_cpu1),
.... );
VHDL: SIGNAL signal_cpu1_to_cpu2 : STD_LOGIC;
SIGNAL signal_cpu2_to_cpu1 : STD_LOGIC;
COMPONENT Nios_system
PORT (
clk : IN std_logic;
reset_n : IN std_logic;
....
in_port_to_the_cpu1_pio_in : IN std_logic;
in_port_to_the_cpu2_pio_in : IN std_logic;
out_port_from_the_cpu1_pio_out : OUT std_logic;
out_port_from_the_cpu2_pio_out : OUT std_logic;
.... );
END COMPONENT;
inst1 : Nios_system
PORT MAP (
clk >= your_clk,
reset_n >= your_reset,
....
in_port_to_the_cpu1_pio_in >= signal_cpu2_to_cpu1;
in_port_to_the_cpu2_pio_in >= signal_cpu1_to_cpu2;
out_port_from_the_cpu1_pio_out >= signal_cpu1_to_cpu2;
out_port_from_the_cpu2_pio_out >= signal_cpu2_to_cpu1;
);
--- Quote End --- It work cris72 thank you.

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