I'm writing a custom DMA machine to read and write data to the host system from FPGA memory. I use the Altera PCIe IP core as end point device in Avalon-MM mode. BAR0 is set as 64bit bar, Avalon-MM slave bus (txs port) also has 64bit address bus. Bar 0 is used to read/write control and status registers. While the port txs of this IP core is connected to my DMA. Completer-Only Endpoint option is disabled.
In linux driver I allocate a memory buffer using dma_allocate_coherent() function. Than I pass the physical address of this buffer and data size to my DMA through the BAR0. After that the DMA starts burst read operation and then stucks because the waitrequest signal on Avalon-MM bus between the DMA and PCIe never falls to 0 and is always held at 1.
So the question is what is the problem can be?
Do I need to told the host system that there will be an DMA request from the pcie device?
Or do I need to apply some special settings to the PCIe IP core?
Thank you for your reply, but i've already found out what was wrong. I needed to enable bus mastering to my PCIE device. Without that the host system doesn't allow DMA transactions to end point.