CyClone IV PLL Dynamic Phase Shifting Probem

[Altera_Forum]

I am experimenting with dynamic phase shifting using a Cyclone IV, DE0-Nano board and Quartus 13.1. My reference input clock is 50Mhz and I have several output clocks all configured for 50Mhz as well. My problem is that when I apply the dynamic phase shift, all the outputs shift simultaneously by the same amount. I am unable to select a single output for shifting via the counter select (cntsel[2:0]) inputs. I'm probably making a simple mistake, but am out of ideas.

[Altera_Forum]

FWIW, I tried the same experiment on a Cyclone V board and the phase shifting worked properly.

[Altera_Forum]

Check that you are using correct cntsel values see Table 5–13 on https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51005.pdf handbook. Cntsel values are different for Cyclone IV and Cyclone V, for eg. if you use cntsel=0 on Cyclone IV you will get phase shift on all outputs and on Cyclone V phase shift will be made on only c0 output.