Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20877 Discussions

Cyclone 10 LP 10CL025 to 10CL006 migration

Zian
Beginner
595 Views

Hi !

I'm creating a PCB layout with a 10CL025 U256, and I'm wondering what will happen if I use in the future a 10CL006 U256 instead of this 10CL025 with the same PCB layout :

- This migration means that some 10CL006 IO pins will be directly connected to GND or VCCINT(1.2V) or VCCA(2.5V)

- For information VCCIO = 3.3V (with 10CL006 and 10CL025)

If these IO pins (connected to GND or VCCINT(1.2V) or VCCA(2.5V)) are specified as inputs with no weak pull-up, I need a confirmation that the 10CL006 FPGA will not have an abnormal behaviour with power voltage on these inputs located in the forbidden zone (between Vil and Vih) : as no FlipFlop (and consequently no CLK rising edge) are connected to these inputs, it should be OK ? No metastability or something else wrong ?

Thanks for answering.

0 Kudos
5 Replies
sstrell
Honored Contributor III
588 Views

You can add a migration device in the Quartus project settings.  Then in the Pin Planner, it will let you know if any of your current assignments will be an issue in the migration device.

0 Kudos
Zian
Beginner
575 Views

Thanks for answering ! I'm already sure that my QSF pin assignments is not an issue because I will not use the IO pins lost in 10CL006 U256 (These pins are connected to GND 1.2V or 2.5V with 10CL025) : I put all these pins in QSF as inputs with no weak pull-up.

I need "a confirmation that the 10CL006 FPGA will not have an abnormal behaviour with power voltage on these inputs located in the forbidden zone (between Vil and Vih) : as no FlipFlop (and consequently no CLK rising edge) are connected to these inputs, it should be OK ? No metastability or something else wrong ?"

0 Kudos
EthanLi
Employee
526 Views

Hi Zian,

 

Please refer to the pin connection guideline for the specific pins like pll/clock pins.

https://www.intel.com/content/www/us/en/docs/programmable/683137/current/clock-and-pll-pins.html 

 

If it is a GPIO pins, it would be OK for leaving it without any pullup or pulldown.

But in general, we suggest to set it as tristate for the safety of circuit.

 

Thanks,

Ethan

 

FvM
Valued Contributor III
517 Views

Hi,
if you select migration devices in Quartus device configuration, the pins that are optionally connected to VCCINT or GND won't be available for any assignment, also not tristate. You can be pretty sure that Quartus configures the pins as necessary.

The previous questions about possible "abnormal behavior" are redundant as well.

0 Kudos
Zian
Beginner
509 Views

I've tried : the report of migration tells that those pins are set as "input tristated".

So without setting migration, I can also set those pins to "input tristated".

0 Kudos
Reply