Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20759 Discussions

Cyclone 10LP Power requirements

ivar_svendsen
Beginner
843 Views

Hello,

I am planning to use Cyclone 10LP (F484 BGA) with a 3.3V Active Serial configuration scheme. All Active Serial configuration pins are part of Bank 1.

I hope to be able to use banks 5, 6 and 8 with 2.5V. However, those banks contains the MSEL, CONF_DONE, INIT_DONE, CRC_ERROR and parallel IO pins.

I have been reading the Cyclone 10LP handbooks and guides, but it is still unclear exactly what is the powerup requirements.

 

Handbook chapter 6.2.1 says:

"After device power up, the device does not release nSTATUS until VCCINT, VCCA, and
VCCIO (for I/O banks in which the configuration and JTAG pins reside) are above the
POR trip point of the device.
• VCCINT and VCCA are monitored for brown-out conditions after device power up.
• VCCA is the analog power to the phase-locked loop (PLL)."

 

The actual POR trip point is not defined anywhere that I can find (not in the device datasheet).
Also, it is not clear which banks are involved.

 

By selecting 3.3V Active Serial, is the banks mentioned (5, 6,  locked to 3.3V, even if their IO are not part of the actual configuration?

 

 

I appreciate any insight to this.

 

Regards,

Ivar Svendsen

 

Labels (2)
0 Kudos
6 Replies
AqidAyman_Intel
Employee
776 Views

Hello Ivar,

Thank you for reaching out Intel FPGA Community.

The POR circuit of the Intel® Cyclone® 10 LP device monitors the VCCINT, VCCA, and VCCIO (of banks 1, 5, 6, and that contain configuration pins during power-on. They must have a monotonic rise to their steady state levels. The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range within 50 ms.

For the recommended operating range for each individual power supply, you can refer to Table 3 in the Intel® Cyclone® 10 LP Device Datasheet.


Regards,

Aqid


0 Kudos
AqidAyman_Intel
Employee
741 Views

Hello Ivar,


Do you need any more support on this?


Regards,

Aqid


0 Kudos
ivar_svendsen
Beginner
681 Views

Hello,

 

I guess I need to make a board and try. It is still not very clear.

 

The device datasheet lists 5 recommended operation voltage ranges (1.2V up to 3.3V), but there is no information on how the chip decide which range the power supply must be stable within, before the end of POR (nSTATUS is released).

There are also no information to what constitute "without plateau".

 

 

Regards,

Ivar Svendsen.

0 Kudos
AqidAyman_Intel
Employee
668 Views

 What I understand, each individual power supply (1.2V up to 3.3V) have their own recommended operating conditions operation as you mentioned. So, they must reach those listed recommended operating range within the power supply ramp up time.


0 Kudos
ivar_svendsen
Beginner
625 Views

Hi,

 

Somehow this thread deviated from the original question:

 

Using 3.3V Active Serial configuration, bank 1 is bound to 3.3V as it is the configuration voltage.

Can I still use 1.5V on banks 5, 6 and 8?


The documentation is somewhat unclear if all banks containing some IO pins (1, 5, 6 and are bound by the same IO voltage standard. They contain configuration pins that are either optional or not used with Active Serial configuration.

 

The following experiment suggests that the configuration voltage standard (set by the MSEL pins) apply to the banks of the active configuration scheme only:

 

1. Create a Quartus project, selecting the target device

2. Using the pin planner, assign the desired voltage standard to each bank.

3. Using the "Device and Pin options" dialog, select the configuration scheme, configuration device IO voltage. I did also select Force VCCIO to be compatible with the configuration IO voltage.

4. Run the IO Assignment Analysis task (Compile design > Analysis & Synthesis)

 

In my case I selected 3.3V Active Serial, and tried selecting 1.8V to all banks (1-8). The IO assignment analysis fails, saying I cannot have 1.8V on bank 1. This makes sense, as the Active Serial IO pins use that bank.

Selecting 3.3V to bank 1 and 1.8V to the other banks, the IO assignment analysis succeeds. This take this as confirmation to my original question.

 

 

Regards,

Ivar Svendsen.

0 Kudos
ivar_svendsen
Beginner
624 Views

Hi,

 

Somehow this thread deviated from the original question:

 

Using 3.3V Active Serial configuration, bank 1 is bound to 3.3V as it is the configuration voltage.

Can I still use 1.5V on banks 5, 6 and 8?


The documentation is somewhat unclear if all banks containing some IO pins (1, 5, 6, and 8.) are bound by the same IO voltage standard. They contain configuration pins that are either optional or not used with Active Serial configuration.

 

The following experiment suggests that the configuration voltage standard (set by the MSEL pins) apply to the banks of the active configuration scheme only:

 

1. Create a Quartus project, selecting the target device

2. Using the pin planner, assign the desired voltage standard to each bank.

3. Using the "Device and Pin options" dialog, select the configuration scheme, configuration device IO voltage. I did also select Force VCCIO to be compatible with the configuration IO voltage.

4. Run the IO Assignment Analysis task (Compile design > Analysis & Synthesis)

 

In my case I selected 3.3V Active Serial, and tried selecting 1.8V to all banks (1-8). The IO assignment analysis fails, saying I cannot have 1.8V on bank 1. This makes sense, as the Active Serial IO pins use that bank.

Selecting 3.3V to bank 1 and 1.8V to the other banks, the IO assignment analysis succeeds. This take this as confirmation to my original question.

 

Unless this is not correct, I consider the case closed.

 

Regards,

Ivar Svendsen.

0 Kudos
Reply